MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 31

• Manufacturer Part Number: MC68040FE33A
• Description: IC MICROPROCESSOR 32BIT 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68040FE33A

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Package: 184CQFP
• Processor Series: M680xx
• Core: CPU32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

applications and high-level languages. The program counter indirect mode also has
indexing and offset capabilities. This addressing mode is typically required to support
position-independent software. Besides these addressing modes, the M68040 provides
index sizing and scaling features.
An instruction’s addressing mode can specify the value of an operand, a register
containing the operand, or how to derive the effective address of an operand in memory.
Each addressing mode has an assembler syntax. Some instructions imply the addressing
mode for an operand. These instructions include the appropriate fields for operands that
use only one addressing mode. Table 1-2 lists a summary of the effective addressing
modes for the M68040. Refer to M68000PM/AD, M68000 Family Programmer’s
Reference Manual, for details on instruction format and addressing modes.
1-10
Register Direct
Register Indirect
Address Register Indirect with Index
Memory Indirect
Program Counter Indirect
Program Counter Indirect with Index
Program Counter Memory Indirect
Absolute Data Addressing
Immediate
Data
Address
Address
Address with Postincrement
Address with Predecrement
Address with Displacement
8-Bit Displacement
Base Displacement
Postindexed
Preindexed
with Displacement
8-Bit Displacement
Base Displacement
Postindexed
Preindexed
Short
Long
Table 1-2. Effective Addressing Modes
Freescale Semiconductor, Inc.
Addressing Modes
For More Information On This Product,
M68040 USER’S MANUAL
Go to: www.freescale.com
([bd,An],Xn,od)
([bd,An,Xn],od)
([bd,PC],Xn,od)
([bd,PC,Xn],od)
(d 8 ,PC,Xn)
(bd,PC,Xn)
(d 8 ,An,Xn)
(bd,An,Xn)
(d16,An)
(d 16 ,PC)
(xxx).W
Syntax
(xxx).L
#<xxx>
(An)+
–(An)
(An)
Dn
An
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