PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 102

• Manufacturer Part Number: PSB3186FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV1.4

• Control Type: HDLC
• Data Rate: 192 Kbps
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

PSB 3186
PSF 3186
Description of Functional Blocks
DU
Figure 54
Structure of Last Octet of Ch2 on DU
When the TIC bus is seized by the ISAC-SX TE, the bus is identified to other devices as
occupied via the DU Ch2 Bus Accessed-bit state ’0’ until the access request is
withdrawn. After a successful bus access, the ISAC-SX TE is automatically set into a
lower priority class, that is, a new bus access cannot be performed until the status "bus
free" is indicated in two successive frames.
If none of the devices connected to the IOM-2 interface request access to the D and C/
I channels, the TIC bus address 7 will be present. The device with this address will
therefore have access, by default, to the D and C/I channels.
Note: Bit BAC (CIX0 register) should be reset by the P when access to the C/I channels
is no more requested, to grant other devices access to the D and C/I channels.
3.7.5.2
S-Bus Priority Mechanism for D-Channel
The S-bus access procedure specified in ITU I.430 was defined to organize D-channel
access with multiple TEs connected to a single S-bus
(Figure
56).
To implement collision detection the D (channel) and E (echo) bits are used. The D-
channel S-bus condition is indicated towards the IOM-2 interface with the S/G bit, i.e. the
availability of the S/T interface D channel is indicated in bit 5 "Stop/Go" (S/G) of the DD
last octet of Ch2 channel
(Figure
55).
S/G = 1 : stop
S/G = 0 : go
Data Sheet
102
2000-08-23