PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 148

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PSB3186FV1.4

Manufacturer Part Number
PSB3186FV1.4
Description
ISDN Interface ISDN
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB3186FV1.4

Control Type
HDLC
Data Rate
192 Kbps
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Package / Case
MQFP-64
Lead Free Status / Rohs Status
 Details
4.1.17
Value after reset: 00
TMD
For general information please refer to
TLP ... Test Loop
The TX path of layer-2 is internally connected with the RX path of layer-2. Data coming
from the layer 1 controller will not be forwarded to the layer 2 controller.
The setting of TLP is only valid if the IOM interface is active.
4.1.18
Value after reset: F3
CIR0
CODR0 ... C/I Code 0 Receive
Value of the received Command/Indication code. A C/I-code is loaded in CODR0 only
after being the same in two consecutive IOM-frames and the previous code has been
read from CIR0.
CIC0 ... C/I Code 0 Change
A change in the received Command/Indication code has been recognized. This bit is set
only when a new code is detected in two consecutive IOM-frames. It is reset by a read
of CIR0.
CIC1 ... C/I Code 1 Change
A change in the received Command/Indication code in IOM-channel 1 has been
recognized. This bit is set when a new code is detected in one IOM-frame. It is reset by
a read of CIR0.
Data Sheet
7
7
TMD -Test Mode Register D-Channel
CIR0 - Command/Indication Receive 0
0
H
H
0
CODR0
0
0
Chapter
148
CIC0
0
3.3.10.
CIC1
0
Detailed Register Description
S/G
0
0
0
BAS
TLP
RD/WR (29)
PSB 3186
PSF 3186
2000-08-23
RD (2E)

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