PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 165

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PSB3186FV1.4

Manufacturer Part Number
PSB3186FV1.4
Description
ISDN Interface ISDN
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB3186FV1.4

Control Type
HDLC
Data Rate
192 Kbps
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Package / Case
MQFP-64
Lead Free Status / Rohs Status
 Details
PSB 3186
PSF 3186
Detailed Register Description
4.3.7
SDS_CR - Control Register Serial Data Strobe
Value after reset: 00
H
7
0
SDS_CR ENS_
ENS_
ENS_
TSS
RD/WR
TSS
TSS+1
TSS+3
(55)
This register is used to select position and length of the strobe signal. The length can be
any combination of two 8-bit timeslot (ENS_TSS, ENS_TSS+1) and one 2-bit timeslot
(ENS_TSS+3).
For general information please refer to
Chapter 3.7.2
and
Chapter
3.7.2.2.
ENS_TSS ... Enable Serial Data Strobe of timeslot TSS
ENS_TSS+1 ... Enable Serial Data Strobe of timeslot TSS+1
0: The serial data strobe signal SDSx is inactive during TSS, TSS+1
1: The serial data strobe signal SDSx is active during TSS, TSS+1
ENS_TSS+3 ... Enable Serial Data Strobe of timeslot TSS+3 (D-Channel)
0: The serial data strobe signal SDSx is inactive during the D-channel (bit7, 6) of TSS+3
1: The serial data strobe signal SDSx is active during the D-channel (bit7, 6) of TSS+3
TSS ... Timeslot Selection
Selects one of 32 timeslots on the IOM-2 interface (with respect to FSC) during which
SDSx
is
active
high
or
provides
a
strobed
BCL
clock
output
(see
SDS_CONF.SDS_BCL). The data strobe signal allows standard data devices to access
a programmable channel.
Data Sheet
165
2000-08-23

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