PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 142

• Manufacturer Part Number: PSB3186FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV1.4

• Control Type: HDLC
• Data Rate: 192 Kbps
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

Note: A change of XFBS will take effect after a receiver command (CMDRD.XME,
RFBS … Receive FIFO Block Size
RFBS
Bit 6
0
0
1
1
Note: A change of RFBS will take effect after a transmitter command (CMDR.RMC,
SRA … Store Receive Address
0 … Receive Address isn’t stored in the RFIFOD
1 … Receive Address is stored in the RFIFOD
XCRC … Transmit CRC
0 … CRC is transmitted
1 … CRC isn’t transmitted
RCRC… Receive CRC
0 … CRC isn’t stored in the RFIFOD
1 … CRC is stored in the RFIFOD
ITF… Interframe Time Fill
Selects the inter-frame time fill signal which is transmitted between HDLC-frames.
0 … idle (continuous ’1’)
1 … flags (sequence of patterns: ‘0111 1110’)
Note: ITF must be set to ’0’ for power down mode.
Data Sheet
CMDRD.XRES, CMDRD.XTF) has been written.
CMDR.RRES,) has been written
In applications with D-channel access handling (collision resolution), the only
possible inter-frame time fill is idle (continuous ’1’). Otherwise the D-channel on
the S/T-bus cannot be accessed
Bit5
0
1
0
1
Block Size Receive
FIFO
32 byte
16 byte
8 byte
4 byte
142
Detailed Register Description
PSB 3186
PSF 3186
2000-08-23