PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 15
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
PSB3186FV1.4
Manufacturer Part Number
PSB3186FV1.4
Description
ISDN Interface ISDN
Manufacturer
Infineon Technologies
Datasheet
1.PSB3186FV1.4.pdf
(207 pages)
Specifications of PSB3186FV1.4
Control Type
HDLC
Data Rate
192 Kbps
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Package / Case
MQFP-64
Lead Free Status / Rohs Status
Details
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IOM-2
IOM-2 Interface
Monitor channel
programming
C/I channels
Layer 1 state machine
Layer 1 state machine
in software
HDLC support
D-channel FIFO size
Reset Signals
Reset Sources
Interrupt Output Signals
Data Sheet
ISAC-SX TE PSB 3186
Double clock (DCL),
bit clock pin (BCL),
serial data strobe (SDS)
Provided
(MON0, 1, 2, ..., 7)
CI0 (4bit),
CI1 (4/6bit)
With changes for
correspondence with the
actual ITU specification
Not possible
D- and B-channel timeslots;
non-auto mode,
transparent mode 1-3,
extended transparent mode
64 bytes cyclic buffer per
direction with
programmable FIFO
thresholds
RES input signal
RSTO output signal
RES Input
Watchdog
C/I Code Change
EAW Pin
Software Reset
INT
low active (open drain) by
default, reprogrammable to
high active (push-pull)
15
ISAC-S TE PSB 2186
Double clock (DCL),
bit clock (BCL),
serial data strobe (SDS)
Provided
(MON0 or 1)
CI0 (4bit),
CI1 (6bit)
Not possible
D-channel timeslot;
auto mode,
non-auto mode,
transparent mode 1-3
2x32 bytes buffer per
direction
RST input/output signal
RST Input
Watchdog
C/I Code Change
EAW Pin
Low active INT
PSB 3186
PSF 3186
2000-08-23
Overview
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