PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 24
PSB3186FV1.4
Manufacturer Part Number
PSB3186FV1.4
Description
ISDN Interface ISDN
Manufacturer
Infineon Technologies
Datasheet
1.PSB3186FV1.4.pdf
(207 pages)
Specifications of PSB3186FV1.4
Control Type
HDLC
Data Rate
192 Kbps
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Package / Case
MQFP-64
Lead Free Status / Rohs Status
Details
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Table 2
Pin No.
MQFP-64
TQFP-64
Miscellaneous
Data Sheet
50
29
43
44
47
48
35
36
58
59
27
6
Symbol
DU
SDS
SX1
SX2
SR1
SR2
XTAL1
XTAL2
EAW
ACL
C768
RSTO
ISAC-SX TE Pin Definitions and Functions (cont’d)
Input (I)
Output (O)
Open Drain
(OD)
I
I
O
O
I
I
I
O
I
O
O
OD
Function
Data Upstream
IOM-2 data signal in upstream direction.
Serial Data Strobe
Programmable strobe signal for time slot and/or D-
channel indication on IOM-2.
S-Bus Transmitter Output (positive)
S-Bus Transmitter Output (negative)
S-Bus Receiver Input
S-Bus Receiver Input
Crystal 1
Connection for a crystal or used as external clock
input. 7.68 MHz clock or crystal required.
Crystal 2
Connection for a crystal. Not connected if an
external clock is supplied to XTAL1.
External Awake
If a falling edge on this input is detected, the ISAC-
SX TE generates an interrupt and, if enabled, a
reset pulse.
Activation LED
This pin can either function as a programmable
output or it can automatically indicate the activated
state of the S interface by a logic ’0’.
An LED with pre-resistance may directly be
connected to ACL.
Clock Output
A 7.68 MHz clock is output to support other devices.
This clock is not synchronous to the S interface.
Reset Output
Low active reset output, either from a watchdog
timeout or programmed by the host.
24
Pin Configuration
PSB 3186
PSF 3186
2000-08-23
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