PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 59

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PSB3186FV1.4

Manufacturer Part Number
PSB3186FV1.4
Description
ISDN Interface ISDN
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB3186FV1.4

Control Type
HDLC
Data Rate
192 Kbps
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Package / Case
MQFP-64
Lead Free Status / Rohs Status
 Details
Table 9
Note: i = input; o = output;
Data Sheet
Signal
FSC
DCL
BCL
DU
DD
1) The S transceiver can be disabled (TR_CONF0.DIS_TR=1) so the IOM clocks
become inputs and with IOM_CR.CLKM the DCL input can be selected to double
clock (0) or single bit clock (1).
2) The direction input/output refers to the direction of the B- and D-channel data
stream across the S-transceiver. Due to the capabilites of the IOM-2 handler the
direction of some other timeslots may be different if this is programmed by the host
(e.g. for data exchange between different devices connected to IOM-2).
IOM-2 Clocks
Function
o: 8 kHz (DIS_TR=0), normal mode
i: 8 kHz (DIS_TR=1), S transceiver disabled
o: 1536 kHz (DIS_TR=0), normal mode
i: 1536/768 kHz (DIS_TR=1), S transceiver disabled
o: 768 kHz
i
o
*2)
*2)
59
Description of Functional Blocks
*1)
*1)
PSB 3186
PSF 3186
2000-08-23

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