PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 108

• Manufacturer Part Number: PSB3186FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV1.4

• Control Type: HDLC
• Data Rate: 192 Kbps
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

3.8.1
The HDLC controller can be programmed to operate in various modes, which are
different in the treatment of the HDLC frame in receive direction. Thus the receive data
flow and the address recognition features can be programmed in a flexible way to satisfy
different system requirements.
The structure of a D-channel two-byte address (LAPD) is shown below:
For address recognition on the D-channel the ISAC-SX TE contains four programmable
registers for individual SAPI and TEI values (SAP1, 2 and TEI1, 2), plus two fixed values
for the “group” SAPI (SAPG = ’FE’ or ’FC’) and TEI (TEIG = ’FF’).
The received C/R bit is excluded from the address comparison. EA is the address field
extension bit which must be set to ’1’ according to HDLC LAPD.
Operating Modes
There are 5 different operating modes which can be selected via the mode selection bits
MDS2-0 in the MODED registers:
Non-Auto Mode (MDS2-0 = ’01x’)
Characteristics:
All frames with valid addresses are accepted and the bytes following the address are
transferred to the = P via RFIFOD. Additional information is available in RSTAD.
Data Sheet
SAPI1, 2, SAPG
High Address Byte
Message Transfer Modes
Full address recognition with one-byte (MDS = ’010’) or
two-byte (MDS = ’011’) address comparison
C/R 0
108
TEI 1, 2, TEIG
Low Address Byte
Description of Functional Blocks
EA
PSB 3186
PSF 3186
2000-08-23