PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 107

• Manufacturer Part Number: PSB3186FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV1.4

• Control Type: HDLC
• Data Rate: 192 Kbps
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

3.8
The ISAC-SX TE contains an HDLC controller for the layer-2 functions of the D- channel
protocol (LAPD). By setting the Enable HDLC channel bits (D_EN_x) in the DCI_CR
register the HDLC controller can access the D or B-channels on IOM-2.
It performs the framing functions used in HDLC based communication: flag generation/
recognition, bit stuffing, CRC check and address recognition.
The FIFO has a size of 64 byte per direction and is implemented as cyclic buffers. The
transceiver reads and writes data sequentially with constant data rate whereas the data
transfer between FIFO and microcontroller uses a block oriented protocol with variable
block sizes.
The configuration, control and status bits related to the HDLC controllers are all assigned
to the following address ranges:
Table 13
D-channel HDLC
Note: For D-channel access the address range 00
Data Sheet
TE PSB 2186), however a single address from this range is sufficient to access
the FIFO as the internal FIFO pointer is incremented automatically independent
from the external address.
HDLC Controllers
HDLC Controller Address Range
FIFO
Address
00
H
-1F
H
107
Config/Ctrl/Status
Registers
20
H
-29
H
Description of Functional Blocks
H
-1F
H
is used (similar as in ISAC-S
PSB 3186
PSF 3186
2000-08-23