PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 179

• Manufacturer Part Number: PSB3186FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV1.4

• Control Type: HDLC
• Data Rate: 192 Kbps
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

For general information please refer to
RSS2, RSS1... Reset Source Selection 2,1
The ISAC-SX TE reset sources for the RSTO output pin can be selected according to
the table below.
• If RSS = ’00’ no above listed reset source is selected and therefore no reset is
• Watchdog Timer
• If RSS = ’10’ is selected the following two reset sources generate a reset pulse of
After a reset pulse generated by the ISAC-SX TE and the corresponding interrupt (WOV
or CIC) the actual reset source can be read from the ISTA.
Data Sheet
Bit 1
generated at RSTO.
After the selection of the watchdog timer (RSS = ’11’) the timer is reset and started.
During every time period of 128 ms the microcontroller has to program the WTC1 and
WTC2 bits in two consecutive bit pattern (see description of the WTC1, 2 bits)
otherwise the watchdog timer expires and a reset pulse of 125 µs
generated. Deactivation of the watchdog timer is only possible with a hardware reset.
125 µs
- External (Subscriber) Awake (EAW)
The EAW input pin serves as a request signal from the subscriber to initiate the awake
function in a terminal and generates a reset pulse (in TE mode only).
- Exchange Awake (C/I Code)
A C/I Code change generates a reset pulse.
0
0
1
1
RSS
Bit 0
0
1
0
1
t  250µs at the RSTO pin:
C/I Code
Change
--
--
x
(reserved)
EAW
--
--
x
Chapter
179
Watchdog
Timer
3.3.8.
--
--
x
Detailed Register Description
t 250 µs is
PSB 3186
PSF 3186
2000-08-23