UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet
UPD784026
Related parts for UPD784026
UPD784026 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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User’s Manual PD784026 Subseries 16/8-bit Single-chip Microcontrollers Hardware PD784020 PD784021 PD784025 PD784026 PD78P4026 Document No. U10898EJ3V0UM00 (3rd edition) Date Published September 1997 N © 1994 Printed in Japan ...
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[MEMO] ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a ...
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They ...
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MAJOR REVISION IN THIS EDITION Page p. 2 Change of 78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM in CHAPTER 1 GENERAL CHAPTER 3 CPU ARCHITECTURE p. 36 • Correction of Figure 3-1 PD784020 Memory Map p. 40 • Addition of caution on ...
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Page CHAPTER 10 TIMER/COUNTER 2 • 10.2 CONFIGURATION p. 275 Addition of caution on reading timer register to (1) Timer register 2 (TM2/TM2W) Deletion of “Also, the count value can be cleared by a match (CR21/CR21W)” from description in (2) ...
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Page CHAPTER 21 LOCAL BUS INTERFACE FUNCTION p. 586 • Addition of cautions on disabling external wait setting to internal ROM area in 21.2.1 Wait Function Control Registers and 21.2.3 Access Waits p. 587 Change of formats in Figure 21-9 ...
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Intended Readership This manual is intended for user engineers who understand the functions of the PD784026 subseries and wish to design application systems using this subseries. Purpose The purpose of this manual is to give users an understanding of the ...
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If there are no particular differences in terms of function: The PD784026 is treated as the representative model. Therefore, when using this manual as the PD784020, 784021, 784025 or 78P4026 user’s manual, PD784026 should be read as PD784020, 784021, ...
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Legend Significance in data notation : High-order digit on left, low-order digit on right Active-low notation : * : Explanation of item marked with * in the text Caution : Item to be especially noted Remark : Supplementary information Numeric ...
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Related Documents Some of the related documents in this document are preliminary versions but are not so specified. Device-related documents Document Name PD784020, 784021 Data Sheet PD784025, 784026 Data Sheet PD78P4026 Preliminary Data Sheet PD784026 Subseries Special Function Register Table ...
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Documents on embedded software (User’s Manuals) Document Name 78K/IV Series Real-Time OS 78K/IV Series OS MX78K4 Other documents Document Name IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC’s Semiconductor Devices Reliability and Quality Control of NEC’s ...
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[MEMO] ...
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CHAPTER 1 GENERAL ................................................................................................................... 1.1 FEATURES ......................................................................................................................................... 1.2 ORDERING INFORMATION AND QUALITY GRADES ............................................................... 1.2.1 Ordering Information ............................................................................................................ 1.2.2 Quality Grades ...................................................................................................................... 1.3 PIN CONFIGURATION (TOP VIEW) .............................................................................................. 1.3.1 Normal Operating Mode ....................................................................................................... 1.3.2 PROM Programming Mode .................................................................................................. 1.4 APPLICATION ...
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Use of RSS Bit ...................................................................................................................... 3.7.4 Stack Pointer (SP) ................................................................................................................ 3.8 GENERAL-PURPOSE REGISTERS ................................................................................................ 3.8.1 Configuration ......................................................................................................................... 3.8.2 Functions ............................................................................................................................... 3.9 SPECIAL FUNCTION REGISTERS (SFRS) .................................................................................. 3.10 CAUTIONS .......................................................................................................................................... CHAPTER 4 CLOCK GENERATOR .............................................................................................. 4.1 CONFIGURATION AND FUNCTION ............................................................................................... ...
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Input/Output Mode / Control Mode Setting ......................................................................... 5.6.3 Operating Status ................................................................................................................... 5.6.4 Internal Pull-Up Resistors .................................................................................................... 5.6.5 Direct LED Drive ................................................................................................................... 5.7 PORT 5 .............................................................................................................................................. 5.7.1 Hardware Configuration ....................................................................................................... 5.7.2 Input/Output Mode/Control Mode Setting ............................................................................ 5.7.3 Operating Status ................................................................................................................... ...
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Basic Operation .................................................................................................................... 8.7.2 Toggle Output ....................................................................................................................... 8.7.3 PWM Output ......................................................................................................................... 8.7.4 PPG Output ........................................................................................................................... 8.7.5 Software Triggered One-Shot Pulse Output ........................................................................ 8.8 EXAMPLES OF USE ........................................................................................................................ 8.8.1 Operation as Interval Timer (1) ............................................................................................ 8.8.2 Operation as Interval Timer ...
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Basic Operation .................................................................................................................... 10.8.2 Toggle Output ....................................................................................................................... 10.8.3 PWM Output ......................................................................................................................... 10.8.4 PPG Output ........................................................................................................................... 10.9 EXAMPLES OF USE ........................................................................................................................ 10.9.1 Operation as Interval Timer (1) ............................................................................................ 10.9.2 Operation as Interval Timer (2) ............................................................................................ 10.9.3 Pulse Width Measurement Operation ...
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PWM Pulse Width Rewrite Cycle Specification .................................................................. 13.4 CAUTION ............................................................................................................................................ CHAPTER 14 A/D CONVERTER ................................................................................................... 373 14.1 CONFIGURATION .............................................................................................................................. 14.2 A/D CONVERTER MODE REGISTER (ADM) .............................................................................. 14.3 OPERATION ....................................................................................................................................... 14.3.1 Basic A/D Converter Operation ............................................................................................ 14.3.2 Select Mode .......................................................................................................................... ...
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Baud Rate Generator Operation .......................................................................................... 16.4.4 Baud Rate Setting in Asynchronous Serial Interface Mode ............................................... 16.5 CAUTIONS .......................................................................................................................................... CHAPTER 17 CLOCKED SERIAL INTERFACE .......................................................................... 435 17.1 FUNCTIONS ........................................................................................................................................ 17.2 CONFIGURATION .............................................................................................................................. 17.3 CONTROL REGISTERS ................................................................................................................... 17.3.1 Clocked Serial Interface ...
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CHAPTER 19 EDGE DETECTION FUNCTION ........................................................................... 485 19.1 EDGE DETECTION FUNCTION CONTROL REGISTERS .......................................................... 19.1.1 External Interrupt Mode Registers (INTM0, INTM1) ........................................................... 19.1.2 Sampling Clock Selection Register (SCS0) ........................................................................ 19.2 EDGE DETECTION FOR PINS P20, P25 AND P26 ................................................................ 19.3 ...
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WHEN INTERRUPT REQUESTS AND MACRO SERVICE ARE TEMPORARILY HELD PENDING ......................................................................................... 20.10 INSTRUCTIONS WHOSE EXECUTION IS TEMPORARILY SUSPENDED BY AN INTERRUPT OR MACRO SERVICE ....................................................... 20.11 INTERRUPT AND MACRO SERVICE OPERATION TIMING .................................................... 20.11.1 Interrupt Acknowledge Processing Time ............................................................................. ...
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CHAPTER 23 RESET FUNCTION ................................................................................................. 641 23.1 RESET FUNCTION ........................................................................................................................... 23.2 CAUTIONS .......................................................................................................................................... CHAPTER 24 PD78P4026 PROGRAMMING .............................................................................. 647 24.1 OPERATING MODES ........................................................................................................................ 24.2 PROM WRITE PROCEDURE .......................................................................................................... 24.3 PROM READING PROCEDURE ..................................................................................................... 24.4 SCREENING OF ONE-TIME PROM PRODUCT .......................................................................... ...
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Figure No. 2-1 Pin Input/Output Circuits ..................................................................................................................... 3-1 PD784020 Memory Map ................................................................................................................... 3-2 PD784021 Memory Map ................................................................................................................... 3-3 PD784025 Memory Map ................................................................................................................... 3-4 PD784026 Memory Map ................................................................................................................... 3-5 Internal RAM Memory Map ................................................................................................................. 3-6 Internal Memory Size Switching Register (IMS) ...
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Figure No. 5-20 Pull-Up Resistor Specification (Port 1) .............................................................................................. 5-21 Example of Direct LED Drive ............................................................................................................. 5-22 Block Diagram of P20 to P24, P26 and P27 (Port 2) ........................................................................ 5-23 Block Diagram of P25 (Port 2) ........................................................................................................... 5-24 Port Specified ...
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Figure No. 5-63 Port Specified as Output Port ............................................................................................................ 5-64 Port Specified as Input Port ............................................................................................................... 6-1 Real-Time Output Port Block Diagram ............................................................................................... 6-2 Real-Time Output Port Control Register (RTPC) Format ................................................................. 6-3 Port 0 Buffer Register (P0H, P0L) Configuration ...
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Figure No. 8-27 Example of Extended PPG Output Cycle .......................................................................................... 8-28 When Timer/Counter 0 is Stopped During PPG Signal Output ........................................................ 8-29 Example of Software Triggered One-Shot Pulse Output .................................................................. 8-30 Interval Timer Operation (1) Timing ................................................................................................... 8-31 Control Register ...
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Figure No. 9-12 To Distinguish Whether One or No Valid Edge Has Been Input with External Event Counter ............................................................................................................... 9-13 Compare Operation in 8-Bit Operating Mode .................................................................................... 9-14 Compare Operation in 16-Bit Operating Mode .................................................................................. 9-15 TM1 Clearance after Match ...
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Figure No. 10-17 TM2 Clearance after Match Detection ............................................................................................... 10-18 Capture Operation in 8-Bit Operating Mode ...................................................................................... 10-19 Capture Operation in 16-Bit Operating Mode .................................................................................... 10-20 TM2 Clearance after Capture Operation ........................................................................................... 10-21 Toggle Output Operation .................................................................................................................... 10-22 PWM Pulse ...
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Figure No. 10-60 One-Shot Timer Operation Start Procedure from Second Time Onward ......................................... 10-61 Operation When Counting Is Started ................................................................................................. 10-62 Example Where Whether One or No Valid Edge Has been Input Cannot Be Distinguished with External Event Counter .................................................................................. ...
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Figure No. 15-1 D/A Converter Block Diagram ............................................................................................................ 15-2 D/A Converter Mode Register (DAM) Format .................................................................................... 15-3 Example of Connecting Capacitors to Reference Voltage Input Pins of D/A Converter ................. 15-4 Example of Buffer Amp Insertion ....................................................................................................... 16-1 Switching Between ...
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Figure No. 17-19 Command ............................................................................................................................................ 17-20 Data ..................................................................................................................................................... 17-21 Acknowledge Signal ............................................................................................................................ 17-22 Busy Signal and Ready Signal ........................................................................................................... 17-23 RELT, CMDT, RELD, CMDD Operation ............................................................................................. 17-24 ACKT Operation .................................................................................................................................. 17-25 ACKE Operation .................................................................................................................................. 17-26 ACKD Operation ................................................................................................................................. 17-27 BSYE ...
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Figure No. 20-17 Macro Service Processing Sequence ................................................................................................ 20-18 Operation at End of Macro Service When VCIE = 0 ......................................................................... 20-19 Operation at End of Macro Service When VCIE = 1 ......................................................................... 20-20 Macro Service Control Word Format ................................................................................................. 20-21 ...
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Figure No. 21-13 Access Wait Function Write Timing .................................................................................................... 21-14 Timing with External Wait Signal ........................................................................................................ 21-15 Refresh Mode Register (RFM) Format .............................................................................................. 21-16 Refresh Area Specification Register (RFA) Format .......................................................................... 21-17 Pulse Refresh Operation in Internal Memory Access ....................................................................... ...
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Table No. 2-1 Port 1 Operating Modes ..................................................................................................................... 2-2 Port 2 Operating Modes ..................................................................................................................... 2-3 Port 3 Operating Modes ( .................................................................................................. 2-4 Port 6 Operating Modes ..................................................................................................................... 2-5 Pin Input/Output Circuit Types and Recommended Connection When ...
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Table No. 9-3 Timer/Counter 1 Pulse Width Measurement Time ............................................................................ 9-4 Maximum Input Frequency and Minimum Input Pulse Width That Can be Counted as Events ................................................................................................................ 10-1 Timer/Counter 2 Intervals ................................................................................................................... 10-2 Timer/Counter 2 Programmable Square-Wave Output Setting Range ............................................ ...
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Table No. 22-3 HALT Mode Release by Maskable Interrupt Request ....................................................................... 22-4 Operating States in STOP Mode ........................................................................................................ 22-5 STOP Mode Release and Operations after Release ........................................................................ 22-6 Operating States in IDLE Mode ......................................................................................................... 22-7 DLE Mode Release and Operations ...
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The PD784026 subseries comprises 78K/IV series products that can perform input/output directly with analog signals. The 78K/IV series comprises 16-bit single-chip microcontrollers equipped with a high-performance CPU that has a function such as accessing a 1M-byte memory space. The PD784026 ...
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SERIES PRODUCT DEVELOPMENT DIAGRAM : Under Mass Production : Under Development Standard Models PD784026 A/D, 16-Bit Timer, Reinforced Power Management ASSP Models PD784908 TM IEBus Controller PD78F4943 Flash Memory for CD-ROM: 56K Bytes PD784915 Software Servo Control Analog Circuit ...
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FEATURES 78K/IV series Pin-compatible with PD78234 subseries High-speed instruction execution • Minimum instruction execution time (25 MHz operation): 160 ns/320 ns/640 ns/1280 ns Instruction set suitable for control applications Data memory extension function (1 M-byte memory space: 2 bank ...
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ORDERING INFORMATION AND QUALITY GRADES 1.2.1 Ordering Information Part Number PD784020GC-3B9 80-pin plastic QFP (14 PD784021GC-3B9 80-pin plastic QFP (14 PD784021GK-BE9 80-pin plastic TQFP (fine pitch) (12 PD784025GC- -3B9 80-pin plastic QFP (14 PD784026GC- -3B9 80-pin plastic QFP (14 ...
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PIN CONFIGURATION (TOP VIEW) 1.3.1 Normal Operating Mode • 80-pin plastic QFP (14 14 mm) PD784020GC-3B9, 784021GC-3B9, 784025GC- PD784026GC- -3B9, 78P4026GC-3B9, 78P4026GC- • 80-pin plastic TQFP (fine pitch) (12 PD784021GK-BE9 • 80-pin ceramic WQFN (14 PD78P4026KK ...
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P00-P07 : Port0 P10-P17 : Port1 P20-P27 : Port2 P30-P37 : Port3 P40-P47 : Port4 P50-P57 : Port5 P60-P67 : Port6 P70-P77 : Port7 TO0-TO3 : Timer Output CI : Clock Input RxD, RxD2 : Receive Data TxD, TxD2 : ...
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PROM Programming Mode (V • 80-pin plastic QFP (14 14 mm) PD78P4026GC-3B9, 78P4026GC- • 80-pin ceramic WQFN (14 14 mm) PD78P4026KK ...
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APPLICATION SYSTEM CONFIGURATION EXAMPLE (PPC) PD784026 RxD Serial Communication TxD Paper Transport INTP0 Detection Fixing Heater ANI0 Temperature Lamp ANI1 Brightness Copy Density ANI2 Adjustment Lever Copy Density ANI3 Correction Lever Reset RESET Circuit 8 CHAPTER 1 GENERAL P11 ...
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BLOCK DIAGRAM Programmable NMI Interrupt INTP0 - INTP5 Controller INTP3 Timer/Counter 0 TO0 (16 Bits) TO1 Timer/Counter 1 INTP0 (16 Bits) INTP1 Timer/Counter 2 INTP2/CI TO2 (16 Bits) TO3 Timer 3 (16 Bits) P00 - P03 Real-Time Output Port ...
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LIST OF FUNCTIONS Part Number Item Number of basic instructions 113 (mnemonics) General-purpose register 8 bits Minimum instruction execution time 160 ns/320 ns/640 ns/1280 ns (at 25 MHz operation) Internal ROM None memory RAM 512 B Memory space 1 ...
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Part Number PD784020 Item Clock output Watchdog timer 1 channel Standby HALT/STOP/IDLE mode Interrupt Hardware source 23 (internal: 16, external: 7 (variable sampling clock input: 1)) Software source BRK instruction, BRKCS instruction, operand error Non-maskable Internal : 1, external : ...
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DIFFERENCES AMONG PD784026 SERIES PRODUCTS 1.7.1 Functional Differences Part Number Item Internal ROM Internal RAM 512 bytes P40 to P47 Operate as address/data bus only P50 to P57 Operate as address bus only P60 to P63 Switchable between output-only ...
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Main Differences between PD784026 Subseries and PD78234 Subseries Series Name Item Number of basic instructions (mnemonics) Minimum instruction execution time Memory space (program/data) Timer/counter Clock output function Watchdog timer Serial interface Interrupts Context switching Priority Counter mode Standby functions ...
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[MEMO] 14 ...
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PIN FUNCTION TABLES 2.1.1 Normal Operating Mode (1) Port pins (1/2) Pin Name Input/Output Dual-Function Pins P00 to P07 Input/output P10 Input/output P11 P12 P13 P14 P15 to P17 P20 Input P21 P22 P23 P24 P25 INTP4/ASCK/SCK1 P26 P27 ...
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Port pins (2/2) Pin Name Input/Output Dual-Function Pins *1 P40 to P47 Input/output *1 P50 to P57 Input/output *2 P60 to P63 Input/output *1 P64 *1 P65 P66 P67 P70 to P77 Input/output * 1. Does not operate as ...
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Pins other than port pins (1/2) Pin Name Input/Output Dual-Function Pins TO0/TO3 Output P34 to P37 CI Input P23/INTP2 RxD Input P30/SI1 RxD2 P13/SI2 TxD Output P31/SO1 TxD2 P14/SO2 ASCK Input P25/INTP4/SCK1 ASCK2 P12/SCK2 SB0 Input/output P33/SO0 SI0 Input ...
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Pins other than port pins (2/2) Pin Name Input/Output Dual-Function Pins ASTB Output CLKOUT CLKOUT Output ASTB RESET Input X1 Input X2 — ANI0-ANI7 Input P70 to P77 ANO0, ANO1 Output AV — REF1 REF2 REF3 ...
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PROM Programming Mode ( PD78P4026 Only: V Pin Name Input/Output V Input PROM programming mode setting PP RESET PROM programming mode setting A0 to A16 Address bus Input/output Data bus CE Input PROM enable input/program pulse ...
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PIN FUNCTIONS 2.2.1 Normal Operating Mode (1) P00 to P07 (Port 0) ... 3-state input/output Port 8-bit input/output port with an output latch, and has direct transistor drive capability. Input/output can be specified bit-wise by means ...
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Port mode P10 and P11 operate as port mode pins when the EN0 and EN1 bits of the PWM control (PWMC) register are cleared (0), and P12 to P14 do the same when the relevant bits of the port ...
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Port P20 Input port / NMI input* P21 Input port / INTP0 input / CR11 capture trigger input / timer/counter 1 count clock / real-time output port trigger signal P22 Input port / INTP1 input / CR22 capture trigger input ...
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CI (Clock Input) The timer/counter 2 external clock input pin. (iv) ASCK (Asynchronous Serial Clock) The external baud rate clock input pin. (v) SCK1 (Serial Clock) The serial clock input/output pin (in 3-wire serial I/O1 mode). (vi) SI0 (Serial ...
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Port mode Each port specified as port mode by the port 3 mode control (PMC3) register can be specified as input/output bit-wise by means of the port 3 mode register (PM3). (b) Control signal input/output mode Pins can be ...
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P50 to P57 (Port 5) ... 3-state input/output Port 8-bit input/output port with an output latch. Input/output can be specified bit-wise by means of the port 5 mode register (PM5). Each pin incorporates a software programmable ...
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Port mode (i) With PD784026 Each port not set in the control mode can be set in the input or output mode in 1-bit units by using the port 6 mode register (PM6). (ii) With PD784021 Of the port ...
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P70 to P77 (Port 7) ... 3-state input/output Port 8-bit input/output port. In addition to operating as an input/output port, it also operates as the A/D converter analog input pins (ANI0 to ANI7). Input/output can be ...
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Caution In the PD78233 and 78237, the TEST pin is the MODE pin and is fixed high. When changing over from the PD78233, 78237, the circuitry can be modified so that this pin is directly connected to V Any modification ...
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PROM Programming Mode ( PD78P4026) (1) V (Programming Power Supply) ... Input PP Input pin that sets the PD78P4026 to the PROM programming mode. When the input voltage of this pin more and the RESET ...
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INPUT/OUTPUT CIRCUITS AND CONNECTION OF UNUSED PINS Table 2-5 shows the input/output circuit types of the pins that have functions, and the connection method when that function is not used. Each input/output circuit type is shown in Figure 2-1. ...
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Table 2-5 Pin Input/Output Circuit Types and Recommended Connection When Not Used (2/2) Pin Name P70/ANI0 to P77/ANI7 ANO0, ANO1 ASTB/CLKOUT RESET TEST AV – AV REF1 REF3 Caution If the input/output mode is undefined for ...
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Type Type 2 IN Schmitt-triggered input with hysteresis characteristics. Type 4 Data P Output N Disable Push-pull output allowing output to be set to high impedance (P-ch & N-ch both off). Type 8-A Pullup ...
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CAUTIONS (1) When connecting unused pins, if the input/output mode is undefined for an input/output dual-function pin, it should be connected to V with a resistor of several tens of k (especially when the reset input pin becomes the ...
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[MEMO] 34 ...
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MEMORY SPACE The PD784026 can access a 1 M-byte memory space. The mapping of the internal data area (special function registers and internal RAM) depends on the LOCATION instruction. A LOCATION instruction must be executed after reset release, and ...
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Figure 3-1 When LOCATION 0 Instruction Is Executed External Memory (960 K Bytes ...
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Figure 3-2 When LOCATION 0 Instruction Is Executed External Memory (960 K Bytes ...
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Figure 3-3 When LOCATION 0 Instruction Is Executed External Memory* (960 K Bytes ...
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Figure 3-4 When LOCATION 0 Instruction Is Executed External Memory* (960 K Bytes ...
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INTERNAL ROM AREA The PD784026 subseries products shown below incorporate ROM which is used to store programs, table data, etc. If the internal ROM area and internal data area overlap when the LOCATION 0 instruction is executed, the internal ...
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BASE AREA The space from 0 to FFFFH comprises the base area. The base area is the object for the following uses: • Reset entry address • Interrupt entry address • CALLT instruction entry address • 16-bit immediate addressing ...
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Vector Table Area The 64-byte area from 00000H to 0003FH is reserved as the vector table area. The vector table area stores the program start addresses used when a branch is made as the result of RESET input or ...
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CALLT Instruction Table Area The 1-byte call instruction (CALLT) subroutine entry addresses can be stored in the 64-byte area from 00040H to 0007FH. The CALLT instruction references this table, and branches to a base area address written in the ...
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INTERNAL DATA AREA The internal data area consists of the internal RAM area and special function register area (see Figures 3-1 to 3-4). The last address of the internal data area can be specified by means of the LOCATION ...
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Internal RAM Area The PD784026 incorporates general-purpose static RAM. This area is configured as follows: Peripheral RAM (PRAM) Internal RAM area Internal high-speed RAM (IRAM) Internal RAM Internal RAM Area Product Name PD784020 512 bytes (0FD00H-0FEFFH) PD784021 2048 bytes ...
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The internal RAM memory map is shown in Figure 3-5. 00FEFFH General-Purpose Register Area 00FE80H 00FE2FH Macro Service Control Word Area 00FE06H 00FE00H Internal High-Speed RAM 00FDFFH 00FD20H 00FD1FH 00FD00H 00FCFFH 00F700H * This area is not available on the ...
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Internal high-speed RAM (IRAM) The internal high-speed RAM (IRAM) allows high-speed accesses to be made. The short direct addressing mode for high- speed accesses can be used on FD20H to FEFFH in this area. There are two kinds of ...
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Special Function Register (SFR) Area The internal peripheral hardware special function registers (SFRs) are mapped onto the area from 0FF00H to 0FFFFH (see Figures 3-1 to 3-4). The area from 0FFD0H to 0FFDFH is mapped as an external SFR ...
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PD78P4026 MEMORY MAPPING The PD78P4026 incorporates 64 K-byte internal ROM and 2048-byte internal RAM, and its memory map is therefore slightly different from that of the PD784025. In order to mask this difference, the PD78P4026 has a function (the ...
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CONTROL REGISTERS Control registers consist of the program counter (PC), program status word (PSW), and stack pointer (SP). 3.7.1 Program Counter (PC) This is a 20-bit binary counter that holds address information on the next program to be executed ...
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Figure 3-8 Program Status Word (PSW) Format 7 Symbol PSWH UF 7 PSWL S The flags are described below. (1) Carry flag (CY) The carry flag records a carry or borrow resulting from an operation. This flag also records the ...
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Example The operation of the overflow flag when an 8-bit addition instruction is executed is shown below. When the addition of 78H (+120) and 69H (+105) is performed, the operation result is E1H (+225), and the two’s complement limit is ...
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Register set selection flag (RSS) The RSS flag specifies the general-purpose registers that function and B, and the general-purpose register pairs (16-bit) that function as AX and BC. This flag is provided to maintain compatibility ...
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Use of RSS Bit Basically, the RSS bit should be fixed all times. The following explanation refers to the case where a 78K/III series program is used, and the program used sets the RSS bit to ...
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Registers used other than those mentioned above are always the same irrespective of the value of the RSS bit. With the NEC assembler (RA78K4), the register operation code generated when the and BC registers are ...
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written in an instruction for which r, r’, rp and rp’ are specified in the operand column, the and BC instructions generate an operation code ...
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Stack Pointer (SP) The stack pointer is a 24-bit register that holds the start address of the stack area (LIFO type: 00000H to FFFFFFH) (see Figure 3-9 used to address the stack area when subroutine processing or ...
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PUSH sfr Instruction SP SP – – 1 PUSH PSW Instruction SP SP – – – 2 CALL, CALLF, CALLT Instruction Stack SP PC19- SP – 1 Undefined PC16 SP – 2 ...
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Figure 3-11 Data Restored from Stack Area POP sfr Instruction POP PSW Instruction PSWH PSWH SP RET Instruction Stack PC19- –* ...
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Cautions 1. With stack addressing, the entire 1 M-byte space can be accessed but a stack area cannot be reserved in the SFR area or internal ROM area. 2. The stack pointer (SP) is undefined after RESET input. Moreover, non-maskable ...
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GENERAL-PURPOSE REGISTERS 3.8.1 Configuration There are sixteen 8-bit general-purpose registers, and two 8-bit general-purpose registers can be used together as a 16-bit general-purpose register. In addition, four of the 16-bit general-purpose registers can be combined with an 8-bit register ...
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Figure 3-13 General-Purpose Register Addresses FEFFH* RBNK0 RBNK1 RBNK2 RBNK3 RBNK4 RBNK5 RBNK6 RBNK7 FE80H* * When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, 0F0000H should be added to the address values shown above. ...
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Functions In addition to being manipulated in 8-bit units, the general-purpose registers can also be manipulated in 16-bit units by pairing two 8-bit registers. Also, four of the 16-bit registers can be combined with an 8-bit register for address ...
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VVP (RG4): • Has a pointer function, and operates as the register that specifies the base address in register indirect addressing, based addressing and based indexed addressing. UUP (RG5): • Has a user stack pointer function, and enables a stack ...
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In addition to the function name that emphasizes the specific function of the register ( AX, BC, VP, UP, DE, HL, VVP, UUP, TDE, WHL), each register can also be written by its ...
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SPECIAL FUNCTION REGISTERS (SFRS) These are registers to which a special function is assigned, such as internal peripheral hardware mode registers, control registers, etc. They are mapped onto the 256-byte space from 0FF00H to 0FFFFH*. * When the LOCATION ...
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Table 3-5 List of Special Function Registers (SFRs) (1/5) *1 Address Special Function Register (SFR) Name 0FF00H Port 0 0FF01H Port 1 0FF02H Port 2 0FF03H Port 3 *2 0FF04H Port 4 *2 0FF05H Port 5 0FF06H Port 6 0FF07H ...
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Table 3-5 List of Special Function Registers (SFRs) (2/5) *1 Address Special Function Register (SFR) Name 0FF20H Port 0 mode register 0FF21H Port 1 mode register 0FF23H Port 3 mode register *2 0FF24H Port 4 mode register *2 0FF25H Port ...
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Table 3-5 List of Special Function Registers (SFRs) (3/5) *1 Address Special Function Register (SFR) Name 0FF50H Timer register 0 0FF51H 0FF52H Timer register 1 0FF53H 0FF54H Timer register 2 0FF55H 0FF56H Timer register 3 0FF57H 0FF5CH Prescaler mode register ...
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Table 3-5 List of Special Function Registers (SFRs) (4/5) *1 Address Special Function Register (SFR) Name 0FF86H Serial shift register 0FF88H Asynchronous serial interface mode register 0FF89H Asynchronous serial interface mode register 2 0FF8AH Asynchronous serial interface status register 0FF8BH ...
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Table 3-5 List of Special Function Registers (SFRs) (5/5) *1 Address Special Function Register (SFR) Name 0FFC4H Memory extension mode register 0FFC5H Hold mode register 0FFC6H Clock output mode register 0FFC7H Programmable wait control register 1 0FFC8H Programmable wait control ...
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CAUTIONS (1) Program fetches cannot be performed from the internal high-speed RAM area (0FD00H to 0FEFFH when the LOCATION 0 instruction is executed; FFD00H to FFEFFH when the LOCATION 0FH instruction is executed). (2) Special function registers (SFRs) Addresses ...
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CONFIGURATION AND FUNCTION The clock generator generates and controls the internal clock and internal system clock supplied to the CPU and internal hardware. The clock generator block diagram is shown in Figure 4-1. EXTC OSTS2 OSTS1 OSTS0 X1 f ...
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Figure 4-2 Clock Oscillator External Circuitry (a) Crystal/ceramic oscillation (b) External clock EXTC bit of .OSTS = PD74HC04, etc. Cautions 1. The oscillator should be as close as possible to the X1 and X2 pins ...
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CONTROL REGISTERS 4.2.1 Standby Control Register (STBC) STBC is a register used to set the standby mode and select the internal system clock. See CHAPTER 22 STANDBY FUNCTION for details of the standby modes. To prevent erroneous entry into ...
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Figure 4-3 Standby Control Register (STBC) Format STBC 0 0 CK1 CK0 Caution If the STOP mode is used when external clock input is used, the EXTC bit of the oscillation stabilization time specification register (OSTS) must ...
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Oscillation Stabilization Time Specification Register (OSTS) OSTS is a register used to specify the operation of the oscillator. The EXTC bit of the OSTS specifies whether a crystal/ ceramic resonator or an external clock is used. The STOP mode ...
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CLOCK GENERATOR OPERATION 4.3.1 Clock Oscillator (1) When using crystal/ceramic oscillation The clock oscillator starts oscillating when the RESET signal is input, and stops oscillation when the STOP mode is set by the standby control register (STBC). Oscillation is ...
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Frequency Divider The frequency divider performs 1/2, 1/4, 1/8 or 1/16 scaling of the clock oscillator output, and supplies the resulting clock to the CPU, watchdog timer, noise elimination circuit, clocked serial interface (CSI), A/D converter, PWM, interrupt control ...
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CAUTIONS The following cautions apply to the clock generator. 4.4.1 When an External Clock Is Input (1) If the STOP mode is used with external clock input, the EXTC bit of the oscillation stabilization time specification register (OSTS) must ...
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When Crystal/Ceramic Oscillation is Used (1) As the oscillator is a high-frequency analog circuit, considerable care is required. The following points, in particular, require attention. • The wiring should be kept as short as possible. • No other signal ...
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Figure 4-7 Incorrect Example of Resonator Connection (a) Wiring of conneted circuits is too long PD748026 (c) Wiring near high alternating current PD784026 X2 X1 High Alternating Current (e) Signal extracted PD784026 ...
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When the device is powered on, and when restoring from the STOP mode, sufficient time must be allowed for the oscillation to stabilize. Generally speaking, the time required for oscillation stabilization is several milliseconds when a crystal resonator is ...
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[MEMO] 84 ...
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DIGITAL INPUT/OUTPUT PORTS The PD784026 is provided with the ports shown in Figure 5-1, enabling various kinds of control to be performed. The function of each port is shown in Table 5-1. For ports use of ...
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Port Name Pin Names Port 0 P00 to P07 • Input or output specifiable bit-wise. • Can also operate as 4-bit real-time output ports (P00 to P03, P04 to P07). • Transistor drive capability. Port 1 P10 to P17 • ...
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PORT 0 Port 8-bit input/output port with an output latch, and has direct transistor drive capability. Input/output can be specified bit-wise by means of the port 0 mode register (PM0). Each pin incorporates a software programmable ...
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Input/Output Mode/Control Mode Setting The port 0 input/output mode is set by means of the port 0 mode register (PM0) as shown in Figure 5-3. Figure 5-3 Port 0 Mode Register (PM0) Format PM0 PM07 PM06 ...
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Operating Status Port input/output port (1) When set as an output port The output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. The output latch ...
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When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction, etc. In this case, too, writes can be performed to the output latch, and data transferred from ...
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Internal Pull-Up Resistors Port 0 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an internal pull-up resistor ...
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Figure 5-7 Pull-Up Resistor Specification (Port 0) Input Buffer Internal Bus (PUO) 92 CHAPTER 5 PORT FUNCTIONS PUO0 Port 0 Mode Register (PM0 P07 P06 P05 P01 P00 ...
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Transistor Drive In port 0, the output buffer high-level side drive capability has been increased, allowing active-high direct transistor drive. An example of the connection is shown in Figure 5-8. CHAPTER 5 PORT FUNCTIONS Figure 5-8 Example of Transistor ...
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PORT 1 Port 8-bit input/output port with an output latch. Input/output can be specified bit-wise by means of the port 1 mode register (PM1). Each pin incorporates a programmable pull-up resistor. This port has direct LED ...
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Hardware Configuration The port 1 hardware configuration is shown in Figures 5-9 to 5-13. Figure 5-9 Block Diagram of P10 and P11 (Port 1) WR Pull-Up Resistor Option Register PUO RD PUO WR Port 1 Mode Register PM1 WR ...
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WR PUO RD PUO WR PM12 Port 1 Mode Register WR PMC12 RD PMC12 Internal Bus WR P12 RD P12 ASCK2, SCK2 Input RD P12 96 CHAPTER 5 PORT FUNCTIONS Figure 5-10 Block Diagram of P12 (Port 1) Pull-Up Resistor ...
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CHAPTER 5 PORT FUNCTIONS Figure 5-11 Block Diagram of P13 (Port 1) WR PUO RD PUO WR PM13 Port 1 Mode Register PM13 WR PMC13 PMC13 RD PMC13 Internal Output Latch WR P13 Bus P13 RD P13 SI2, RxD2 Input ...
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WR PUO RD PUO WR PM14 Port 1 Mode Register WR PMC14 RD PMC14 Internal TxD2/SO2 Output Bus WR P14 RD P14 RD P14 Figure 5-13 Block Diagram of P15 to P17 (Port 1) WR PUO RD PUO WR PM1 ...
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Input/Output Mode/Control Mode Setting The port 1 input/output mode is set for each pin by means of the port 1 mode register (PM1) as shown in Figure 5-14. In addition to their input/output port function, P10 and P11 also ...
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Figure 5-15 Port 1 Mode Control Register (PMC1) Format PMC1 PMC14 100 CHAPTER 5 PORT FUNCTIONS Address PMC13 PMC12 0 0 0FF41H PMC12 P12 Pin Control Mode Specification 0 ...
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Operating Status Port input/output port. Pins P10 and P11 have a dual function as PWM signal output pins, and pins P12 to P14 have a dual function as serial interface pins. (1) When set as an ...
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When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction, etc. In this case, too, writes can be performed to the output latch, and data transferred from ...
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When specified as control signal input/output P10 and P11 (by setting (1) the ENn bit ( the PWM control register(PWMC)) and P12 to P14 (by setting (1) bits of the port 1 mode control ...
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Internal Pull-Up Resistors Port 1 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an internal pull-up resistor ...
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Figure 5-20 Pull-Up Resistor Specification (Port 1) Input Buffer Internal Bus (PUO) 5.3.5 Direct LED Drive In port 1, the output buffer low-level side drive capability has been reinforced allowing active-low direct LED drive. An example of such use is ...
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PORT 2 Port 8-bit input-only port. P22 to P27 incorporate a software programmable pull-up resistor. As well as operating as input ports, port 2 pins also operate as control signal input pins, such as external interrupt ...
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CHAPTER 5 PORT FUNCTIONS (iii) CI (Clock Input) The timer/counter 2 external clock input pin. (iv) ASCK (Asynchronous Serial Clock) The external baud rate clock input pin. (v) SCK1 (Serial Clock 1) The serial clock input/output pin (in 3-wire serial ...
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Hardware Configuration The port 2 hardware configuration is shown in Figure 5-22. Figure 5-22 Block Diagram of P20 to P24, P26 and P27 (Port 2) WR PUO RD PUO RD P2n Internal Various Interrupt Bus Control Signals RD P27 ...
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CHAPTER 5 PORT FUNCTIONS Figure 5-23 Block Diagram of P25 (Port 2) WR PUO PU02 RD PUO Internal Bus INTP4 Input RD P25 V DD SCK1 Output Mode SCK1 Output ASCK/SCK1 Input Edge Detection Circuit P25/ASCK/SCK1 109 ...
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Input Mode/Control Mode Setting Port input-only port, and there is no register for setting the input mode. Also, control signal input is always possible, and therefore the signal to be used is determined by the control ...
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Figure 5-26 Pull-Up Specification (Port 2) Input Internal Buffer Bus Caution As P22 to P26 are not pulled up immediately after a reset, an interrupt request flag may be set depending on the function of the dual-function pins (INTP1 to ...
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PORT 3 Port 8-bit input/output port with an output latch. Input/output can be specified bit-wise by means of the port 3 mode register (PM3). Each pin incorporates a software programmable pull-up resistor. In addition to its ...
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Control signal input/output mode Pins can be set as control pins bit-wise by setting the port 3 mode control register (PMC3). (i) RxD (Receive Data)/SI1 (Serial Input 1) RxD is the asynchronous serial interface serial data input pin. SI1 ...
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Hardware Configuration The port 3 hardware configuration is shown in Figures 5-27 to 5-30. WR PUO RD PUO WR Port 3 Mode Register PM30 WR PMC30 RD PMC30 Internal WR Bus P30 RD P30 SI1, RxD Input RD P30 ...
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CHAPTER 5 PORT FUNCTIONS Figure 5-28 Block Diagram of P31 and P34 to P37 (Port 3) WR Pull-Up Resistor Option Register PUO PUO3 RD PUO WR PM3n Port 3 Mode Register PM3n WR PMC3n PMC3n RD PMC3n Internal Bus TO, ...
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WR PUO RD PUO WR PM32 Port 3 Mode Register WR PMC32 RD PMC32 Internal WR Bus P32 RD P32 SCK0 Input RD P32 116 CHAPTER 5 PORT FUNCTIONS Figure 5-29 Block Diagram of P32 (Port 3) Pull-Up Resistor Option ...
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CHAPTER 5 PORT FUNCTIONS Figure 5-30 Block Diagram of P33 (Port 3) WR Pull-Up Resistor Option Register PUO PUO3 RD PUO WR Port 3 Mode Register PM33 PM33 WR PMC33 PMC33 RD PMC33 Internal Bus SB0 Output SO0 Output WR ...
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Input/Output Mode/Control Mode Setting The port 3 input/output mode is set for each pin by means of the port 3 mode register (PM3) as shown in Figure 5-31. In addition to their input/output port function, port 3 pins also ...
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Figure 5-32 Port 3 Mode Control Register (PMC3) Format PMC3 PMC37 PMC36 PMC35 PMC34 PMC33 CHAPTER 5 PORT FUNCTIONS Address PMC32 PMC31 PMC30 0FF43H PMC30 P30 Pin Control Mode Specification 0 Input/output ...
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Operating Status Port input/output port, with a dual function as various control pins. (1) When set as an output port The output latch is enabled, and data transfers between the output latch and accumulator are performed ...
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When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can be performed to the output latch, and data transferred from the ...
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When specified as control signal input/output By setting (1) bits of the port 3 mode control register (PMC3), port 3 can be used as control signal input or output bit-wise irrespective of the setting of the port 3 mode ...
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Internal Pull-Up Resistors Port 3 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an internal pull-up resistor ...
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Input Buffer Internal Bus (PUO) 124 CHAPTER 5 PORT FUNCTIONS Figure 5-37 Pull-Up Specification (Port 3) PUO3 Port 3 Mode Register (PM3 P30 P31 P32 P36 P37 ...
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PORT 4 Port 8-bit input/output port with an output latch. Input/output can be specified bit-wise by means of the port 4 mode register (PM4). Each pin incorporates a software programmable pull-up resistor. This port has direct ...
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Input/Output Mode / Control Mode Setting The port 4 input/output mode is set for each pin by means of the port 4 mode register (PM4) as shown in Figure 5-39. When port 4 is used as the address/data bus, ...
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Operating Status Port input/output port, with a dual function as the address/data bus (AD0 to AD7). (1) When set as an output port The output latch is enabled, and data transfers between the output latch and ...
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When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can be performed to the output latch, and data transferred from the ...
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Internal Pull-Up Resistors Port 4 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an internal pull-up resistor ...
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Input Buffer Internal Bus (PUO) 130 CHAPTER 5 PORT FUNCTIONS Figure 5-43 Pull-Up Specification (Port 4) PUO4 Port 4 Mode Register (PM4 P40 P41 P42 P46 P47 ...
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Direct LED Drive In port 4, the output buffer low-level side drive capability has been reinforced, allowing active-low direct LED drive. An example of such use is shown in Figure 5-44. CHAPTER 5 PORT FUNCTIONS Figure 5-44 Example of ...
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PORT 5 Port 8-bit input/output port with an output latch. Input/output can be specified bit-wise by means of the port 5 mode register (PM5). Each pin incorporates a software programmable pull-up resistor. This port has direct ...
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Input/Output Mode/Control Mode Setting The port 5 input/output mode is set for each pin by means of the port 5 mode register (PM5) as shown in Figure 5-46. When port 5 pins can be used as port or address ...
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Operating Status Port input/output port, with a dual function as the address bus (A8 to A15). (1) When set as an output port The output latch is enabled, and data transfers between the output latch and ...
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When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can be performed to the output latch, and data transferred from the ...
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Internal Pull-Up Resistors Port 5 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an internal pull-up resistor ...
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CHAPTER 5 PORT FUNCTIONS Figure 5-50 Pull-Up Specification (Port 5) Input Buffer Internal Bus (PUO) PUO5 V DD Port 5 Mode Register (PM5) P50 P51 P52 P56 P57 137 ...
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Direct LED Drive In port 5, the output buffer low-level side drive capability has been reinforced, allowing active-low direct LED drive. An example of such use is shown in Figure 5-51. 138 CHAPTER 5 PORT FUNCTIONS Figure 5-51 Example ...
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PORT 6 Port 8-bit input/output port with an output latch (in the PD784021, P60 to P63 are output-only port pins). P60 to P67 (P64 to P67 in the PD784021) incorporate a software programmable pull-up resistor. In ...
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Hardware Configuration The port 6 hardware configuration is shown in Figures 5-52 to 5-55. Figure 5-52 Block Diagram of P60 to P63 (Port 6) WR PUO Pull-Up Resistor Option Register PUO6 RD PUO WR PM6n Port 6 Mode Register ...
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CHAPTER 5 PORT FUNCTIONS Figure 5-53 Block Diagram of P64 and P65 (Port 6) WR Pull-Up Resistor Option Register PUO PUO6 RD PUO WR PM64, PM65 Port 6 Mode Register PM64 (PM65) External Extension Mode RD Signal (WR Signal) Internal ...
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WR PUO RD PUO WR PM66 Port 6 Mode Register Hold Enabled Mode External Wait Specification Internal WR PM66 Bus RD OUT Wait Input Hold Request Input RD IN 142 CHAPTER 5 PORT FUNCTIONS Figure 5-54 Block Diagram of P66 ...
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CHAPTER 5 PORT FUNCTIONS Figure 5-55 Block Diagram of P67 (Port 6) WR Pull-Up Resistor Option Register PUO PUO6 RD PUO WR PM67 Port 6 Mode Register PM67 Hold Enabled Mode Refresh Mode Internal Refresh Signal Bus Hold Acknowledge Signal ...
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Input/Output Mode/Control Mode Setting The port 6 input/output mode is set by means of the port 6 mode register (PM6) as shown in Figure 5-56. Operations for operating port 6 as control pins are shown in Table 5-10. In ...
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Control signal input/output mode (i) A16 to A19 (Address Bus) Upper address bus output pins when the external memory space is extended (10000H-FFFFFH). These pins operate in accordance with the memory extension mode register (MM). (ii) RD (Read Strobe) ...
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Figure 5-56 Port 6 Mode Register (PM6) Format PM6 PM67 PM66 PM65 PM64 Remark In the PD784021, the low-order 4 bits of port 6 (P60 to P63) are output-only ports. 5.8.3 Operating Status Port ...
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When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can be performed to the output latch, and data transferred from the ...
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Internal Pull-Up Resistors P60 to P67 (P64 to P67 in the PD784021) incorporate pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not ...
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CHAPTER 5 PORT FUNCTIONS Figure 5-60 Pull-Up Specification (Port 6) Input Buffer Internal Bus (PUO) PUO6 V DD Port 6 Mode Register (PM6) P64 P65 P66 P67 149 ...
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PORT 7 Port 8-bit input/output port. In addition to operating as an input/output port, it also operates as the A/D converter analog input pins (ANI0 to ANI7). Input/output can be specified bit-wise by means of the ...
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Input/Output Mode/Control Mode Setting The port 7 input/output mode is set for each pin by means of the port 7 mode register (PM7) as shown in Figure 5-62. In addition to the operation of port input/output ...
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Operating Status Port input/output port, with a dual function as the A/D converter analog input pins (ANI0 to ANI7). (1) When set as an output port The output latch is enabled, and data transfers between the ...
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When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can be performed to the output latch, and data transferred from the ...
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PORT OUTPUT CHECK FUNCTION The PD784026 has a function for reading and testing output port pin levels in order to improve the reliability of application systems therefore possible to check the output data and the actual pin ...
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CAUTIONS (1) All port pins become high-impedance after RESET signal input (internal pull-up resistors are disconnected from the pins). If there is a problem with pins becoming high-impedance during RESET input, this should be handled with external circuitry. (2) ...
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As port input-only port, a comparison of the pin status with the output latch contents using the CHKL or CHKLA instruction will always show a match. Therefore, executing these instructions on port 2 is actually ineffective. ...
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CHAPTER 6 REAL-TIME OUTPUT FUNCTION 6.1 CONFIGURATION AND FUNCTION The real-time output function is implemented by hardware, including primarily port 0 and the port 0 buffer registers (P0H, P0L), shown in Figure 6-1. The real-time output function refers to the ...
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RTPC BYTE P0MH EXTR TRGP0 P0ML INTC11 P0MH INTP0 INTC10 Selector P0ML EXTR TRGP0 Figure 6-1 Real-Time Output Port Block Diagram Internal Bus P0H BYTE 4-Bit Real-Time Output (P0H) 4-Bit Real-Time Output (P0L) Selector 8-Bit Real-Time Output (P0) P07 P06 ...
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REAL-TIME OUTPUT PORT CONTROL REGISTER (RTPC) The RTPC is an 8-bit register that specifies the function of port 0. RTPC can be read or written 8-bit manipulation instruction or bit-manipulation instruction. Figure 6-2 shows the format ...
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REAL-TIME OUTPUT PORT ACCESSES The port 0 buffer registers (P0H, P0L) are mapped onto mutually independent addresses in the SFR area as shown in Figure 6-3. When the 4-bit 2-channel real-time output function is specified, data can be set ...