UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 560

• Manufacturer Part Number: UPD784026
• Description: 16/8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

20.7.1 Vectored Interrupt
counter (PC) are saved in that order to the stack, the IE flag is cleared (0) (the interrupt disabled state is set), and the in-
service priority register (ISPR) bit corresponding to the priority of the acknowledged interrupt is set (1). Also, data in the
vector table predetermined for each interrupt request is loaded into the PC, and a branch is performed. The return from
a vectored interrupt is performed by means of the RETI instruction.
20.7.2 Context Switching
register.
by 3 bits of the low-order address (even address) of the corresponding vector table address is selected.
the same time the contents of the PC and program status word (PSW) up to that time are saved in the register bank and
a branch is made to the interrupt service program.
520
When a vectored interrupt maskable interrupt request is acknowledged, the program status word (PSW) and program
Caution When a maskable interrupt is acknowledged by vectored interrupt, the RETI instruction must be used
Initiation of the context switching function is enabled by setting (1) the context switching enable flag of the interrupt control
When an interrupt request for which the context switching function is enabled is acknowledged, the register bank specified
The vector address stored beforehand in the selected register bank is transferred to the program counter (PC), and at
2 Save
(Temporary
Register
Bit 8-11)
to return from the interrupt. Subsequent interrupt acknowledgment will not be performed normally
if a different instruction is used.
PC
1 Save
Figure 20-11 Context Switching Operation by Generation of an Interrupt Request
19-16
PSW
7 Transfer
0000B
Temporary Register
5 Save
PC
15-0
Vector Table
6 Exchange
CHAPTER 20 INTERRUPT FUNCTIONS
W
V
U
T
Register Bank n (n = 0 to 7)
n
R5
R7
A
B
D
H
UP
3 Register Bank Switching
VP
(RSB0-RSB2
R4
R6
X
C
E
L
4
(
RSS
IE
n)
0
0
)
Register Bank
(0 to 7)