UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 548

• Manufacturer Part Number: UPD784026
• Description: 16/8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

20.3.3 In-Service Priority Register (ISPR)
being processed. When a maskable interrupt request is acknowledged, the bit corresponding to the priority of that interrupt
request is set (1), and remains set until the service program ends. When a non-maskable interrupt is acknowledged, the
bit corresponding to the priority of that non-maskable interrupt is set (1), and remains set until the service program ends.
to the highest-priority interrupt request is automatically cleared (0) by hardware.
508
The ISPR shows the priority level of the maskable interrupt currently being processed and the non-maskable interrupt
When an RETI instruction or RETCS instruction is executed, the bit, among those set (1) in the ISPR, that corresponds
The contents of the ISPR are not changed by execution of an RETB or RETCSB instruction.
RESET input clears the ISPR register to 00H.
Caution In-service priority register (ISPR) is a read-only register. There is a risk of misoperation if a write is
ISPR
NMIS
performed on this register.
7
WDTS
6
5
0
Figure 20-3 In-Service Priority Register (ISPR) Format
4
0
CHAPTER 20 INTERRUPT FUNCTIONS
ISPR3
3
ISPR2
2
ISPR1
1
ISPR0
0
ISPRn
WDTS
NMIS
0FFA8H
Address
0
1
0
1
0
1
Priority Level
Priority n interrupt not being acknowledged
Priority n interrupt being acknowledged
NMI Processing State
NMI interrupt not being acknowledged
NMI interrupt being acknowledged
Watchdog Timer Interrupt Processing State
Watchdog timer interrupt not being
acknowledged
Watchdog timer interrupt being
acknowledged
On Reset
00H
R/W
R
(n = 0-3)