UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 453

• Manufacturer Part Number: UPD784026
• Description: 16/8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

16.2.6 Reception
and sampling of the RxD input pin is performed.
rate generator control register (BRGC).
is output on the m’th count. If the RxD pin input is low when sampled again by this start timing signal, the input is recognized
as a start bit, the divide-by-m counter is initialized and the count is started, and data sampling is performed. When the
character data, parity bit and stop bit are detected following the start bit, reception of one data frame ends.
and a reception completion interrupt (INTSR) is generated.
was cleared (0) when the error occurred,
contents of RXB and ASIS are not changed, and no INTSR or INTSER interrupt is generated.
When the RXE bit of the asynchronous serial interface mode register (ASIM) is set (1), receive operations are enabled
RxD input pin sampling is performed using the serial clock (divide-by-m counter input clock) specified by ASIM and band
When the RxD pin input is driven low, the divide-by-m counter starts counting and a data sampling start timing signal
When reception of one data frame ends, the receive data in the shift register is transferred to the receive buffer, RXB,
If an error occurs, the receive data in which the error occurred is still transferred to RXB. If bit 1 (ISRM) of the ASIM
INTSR is generated. If the ISRM was set (1), INTSR is not generated.
If the RXE bit is cleared (0) during a receive operation, the receive operation is stopped immediately. In this case the
Cautions 1. The receive buffer (RXB) must be read even if there is a receive error. If RXB is not read, an overrun
RxD (Input)
2. To disable the reception completion interrupt when a reception error occurs, make sure that wait
Figure 16-7 Asynchronous Serial Interface Reception Completion Interrupt Timing
INTSR
error will occur when the next data is received, and the receive error state will continue indefinitely.
time equivalent to two pulses of the clock that serves as the reference of the baud rate clock elapse
after the reception error occurs until the receive buffers (RXB, RXB2) are read. If the wait time
is not inserted, the reception completion interrupt occurs even when it is disabled.
The wait time equivalent to two pulses of the clock that serves as the reference of the baud rate
clock can be calculated by the following expression:
Wait time =
Remark f
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
n : Value of baud rate generator control registers (BRGC, BRGC2) to select tap of 12-bit
XX
: Oscillation frequency
2
f
n+3
XX
prescaler (n = 0 to 11)
START
D0
D1
D2
D6
D7
Parity
STOP
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