UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 610

• Manufacturer Part Number: UPD784026
• Description: 16/8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

20.13 CAUTIONS
(1) The in-service priority register (ISPR) is read-only. Writing to this register may result in misoperation.
(2) The watchdog timer mode register (WDM) can only be written to with a dedicated instruction (MOV WDM, #byte).
(3) The RETI instruction must not be used to return from a software interrupt caused by a BRK instruction.
(4) The RETCS instruction must not be used to return from a software interrupt caused by a BRKCS instruction.
(5) When a maskable interrupt is acknowledged by vectored interrupt, the RETI instruction must be used to return from
(6) The RETCS instruction must be used to return from a context switching interrupt. Subsequent interrupt related
(7) Macro service requests are acknowledged and processed even during execution of a non-maskable interrupt service
(8) The RETI instruction must be used to return from a non-maskable interrupt. Subsequent interrupt acknowledgment
(9) Non-maskable interrupts are always acknowledged, except during non-maskable interrupt service program execution
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The RETB instruction must be used.
The RETCSB instruction must be used.
the interrupt. Subsequent interrupt related operations will not be performed normally if a different instruction is used.
operations will not be performed normally if a different instruction is used.
program. If you do not want macro service processing to be performed during a non-maskable interrupt service program,
you should manipulate the interrupt mask register in the non-maskable interrupt service program to prevent macro
service generation.
will not be performed normally if a different instruction is used. For details on how to resume program execution from
the initial status after the non-maskable interrupt has been acknowledged, see 20.12 RESTORING INTERRUPT
FUNCTION TO INITIAL STATE.
(except when a high non-maskable interrupt request is generated during execution of a low-priority non-maskable
interrupt service program) and for a certain period after execution of the special instructions shown in 20.9. Therefore,
a non-maskable interrupt will be acknowledged even when the stack pointer (SP) value is undefined, in particular after
reset release, etc. In this case, depending on the value of the SP, it may happen that the program counter (PC) and
program status word (PSW) are written to the address of a write-inhibited special function register (SFR) (see Table
3-5 in 3.9 SPECIAL FUNCTION REGISTERS (SFR)), and the CPU becomes deadlocked, or the PC and PSW are
written to an unexpected signal is output from a pin, or an address is which RAM is not mounted, with the result that
the return from the non-maskable interrupt service program is not performed normally and an inadvertent program loop
occurs.
Therefore, the program following RESET release must be as follows.
STRT:
CSEG AT 0
DW
CSEG BASE
LOCATION 0FH; or LOCATION 0
MOVG SP, #imm24
STRT
CHAPTER 20 INTERRUPT FUNCTIONS