UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 462

• Manufacturer Part Number: UPD784026
• Description: 16/8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

16.3.5 Operation When Reception Only is Enabled
The receive operation starts when the CRXE1 changes from “0” to “1”, or when a read from shift register (SIO1) is performed.
(1) When the internal clock is selected as the serial clock
(2) When an external clock is selected as the serial clock
422
A receive operation is performed when the CRXE1 bit of the clocked serial interface mode register (CSIM1) is set (1).
When reception starts, the serial clock is output from the SCK1 pin and the SI1 pin data is fetched in sequence into
shift register (SIO1) in synchronization with the rise of the serial clock.
There is a delay of up to one SCK1 clock cycle between the start of reception and the first fall of SCK1.
If reception is disabled during the receive operation (by clearing (0) the CRXE1 bit), SCK1 clock output is stopped and
the receive operation is discontinued on the next rise of SCK1. In this case an interrupt request (INTCSI1) is not
generated, and the contents of the SIO1 are undefined.
When reception starts, the SI1 pin data is fetched into shift register (SIO1) in synchronization with the rise of the serial
clock input to the SCK1 pin after the start of reception. If reception has not started, shift operations are not performed
even if the serial clock is input to the SCK1 pin.
If reception is disabled during the receive operation (by clearing (0) the CRXE1 bit), the receive operation is discontinued
and subsequent SCK1 input is ignored. In this case an interrupt request (INTCSI1) is not generated.
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O