UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 557

• Manufacturer Part Number: UPD784026
• Description: 16/8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Cautions 1. Macro service requests are acknowledged and processed even during execution of a non-
2. The RETI instruction must be used to return from a non-maskable interrupt. Subsequent interrupt
3. Non-maskable interrupts are always acknowledged, except during non-maskable interrupt service
maskable interrupt service program. If you do not want macro service processing to be performed
during a non-maskable interrupt service program, you should manipulate the interrupt mask
register in the non-maskable interrupt service program to prevent macro service generation.
acknowledgment will not be performed normally if a different instruction is used. For details on
how to resume program execution from the initial status after the non-maskable interrupt has been
acknowledged, see 20.12 RESTORING INTERRUPT FUNCTION TO INITIAL STATE.
program execution (except when a high non-maskable interrupt request is generated during
execution of a low-priority non-maskable interrupt service program) and for a certain period after
execution of the special instructions shown in 20.9. Therefore, a non-maskable interrupt will be
acknowledged even when the stack pointer (SP) value is undefined, in particular after reset release,
etc. In this case, depending on the value of the SP, it may happen that the program counter (PC)
and program status word (PSW) are written to the address of a write-inhibited special function
register (SFR) (see Table 3-5 in 3.9 Special Function Registers (SFR)), and the CPU becomes
deadlocked, or an unexpected signal is output from a pin, or the PC and PSW are written to an
address in which RAM is not mounted, with the result that the return from the non-maskable
interrupt service program is not performed normally and an inadvertent program loop occurs.
Therefore, the program following RESET release must be as shown below.
STRT:
CSEG AT 0
DW
CSEG BASE
LOCATION
MOVG SP, #imm24
STRT
CHAPTER 20 INTERRUPT FUNCTIONS
0FH; or LOCATION 0
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