UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 530

• Manufacturer Part Number: UPD784026
• Description: 16/8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

19.3 P21 PIN EDGE DETECTION
selection register (SCS0). In digital noise elimination, input is sampled using the f
the same at least 4 times in succession (if it is the same only 3 or fewer times in succession), it is eliminated as noise.
Therefore, the level must be maintained for at least 4 f
490
In P21 edge detection, digital noise elimination is performed using the clock (f
Remark When the pulse width of a signal with a comparatively long pulse width and a lot of noise, such as an infrared
Cautions 1. Since digital noise elimination is performed with the f
P21 Input Signal after
Noise Elimination
Falling Edge
Rising Edge
remote count reception signal, is measured, or when a signal is input in which oscillation occurs when an edge
occurs, as with switch input chattering, for instance, it is better to set the sampling clock to low speed with
the sampling clock selection register (SCS0). If the sampling clock is high-speed, there will be a reaction to
the short-pulse noise components as well, and the program will frequently have to check whether the input
is noise or a signal. However, by slowing down the sampling clock, reaction to short pulse width noise is
eliminated and thus the program does not have to check so frequently, and can thus be simplified.
2. If the input pulse width is 3 to 4 f
3. If noise input to the pin is synchronized with the f
P21 Input
between input of an edge to the pin and the point at which the edge is actually detected.
Therefore, to ensure reliable operation, the level should be held for at least 4 clocks.
recognized as noise. If there is a possibility of such noise being input, noise should be eliminated
by adding a filter to the input pin.
f
SMP
Digital noise
elimination with f
CHAPTER 19 EDGE DETECTION FUNCTION
Figure 19-5 P21 Pin Edge Detection
SMP
clock
SMP
SMP
clocks, it is uncertain whether a valid edge will be detected.
clock cycles in order to be recognized as a valid edge.
SMP
SMP
clock, there is a delay of 3 to 4 f
clock in the PD784026, it may not be
SMP
SMP
) specified by the sampling clock
clock, and if the input level is not
SMP
clocks