UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 448

• Manufacturer Part Number: UPD784026
• Description: 16/8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(2) Asynchronous serial interface status register (ASIS),
408
* To disable the reception completion interrupt when a reception error occurs, make sure that wait time equivalent to
Caution An asynchronous serial interface mode register (ASIM/ASIM2) rewrite should not be performed during
Asynchronous serial interface status register 2 (ASIS2)
The ASIS and ASIS2 contain flags that indicate the error contents when a receive error occurs. Flags are set (1) when
a receive error occurs, and cleared (0) when data is read from the receive buffer (RXB/RXB2). If the next data is received
before RXB/RXB2 is read, the overrun error flag (OVE/OVE2) is set (1), and the other error flags are cleared (0) (if
there is an error in the next data, the corresponding error flag is set (1)).
These registers can be read only by an 8-bitmanipulation instruction or bit manipulation instruction. The format of ASIS
and ASIS2 is shown in Figure 16-4.
These registers are cleared to 00H by RESET input.
two pulses of the clock that serves as the reference of the baud rate clock elapse after the reception error occurs
until the receive buffers (RXB, RXB2) are read. If the wait time is not inserted, the reception completion interrupt
occurs even when it is disabled.
The wait time equivalent to two pulses of the clock that serves as the reference of the baud rate clock can be calculated
by the following expression:
Wait time =
Remark f
a transmit operation. If an ASIM/ASIM2 register rewrite is performed during a transmit operation,
subsequent transmit operations may not be possible (normal operation is restored by RESET input).
Software can determine whether transmission is in progress by using a transmission completion
interrupt (INTST/INTST2) or the interrupt request flag (STIF/STIF2) set by INTST/INTST2.
n : Value of baud rate generator control registers (BRGC, BRGC2) to select tap of 12-bit prescaler (n
XX
: Oscillation frequency
2
f
n+3
XX
= 0 to 11)
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O