UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 455

• Manufacturer Part Number: UPD784026
• Description: 16/8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

16.3 3-WIRE SERIAL I/O MODE
input (SI). Handshaking lines are required when a number of devices are connected.
16.3.1 Configuration in 3-Wire Serial I/O Mode
Cautions 1. The contents of the asynchronous serial interface status register (ASIS) are cleared (0) by reading
The 3-wire serial I/O mode is used to communicate with devices that incorporate a conventional clocked serial interface.
Basically, communication is performed using three lines: the serial clock (SCK), serial data output (SO), and serial data
* Handshaking lines
The block diagram in the 3-wire serial I/O mode is shown in Figure 16-10.
3-wire serial I/O
2. The RXB must be read even if there is a receive error. If RXB is not read, an overrun error will
3. To disable the reception completion interrupt when a reception error occurs, make sure that wait
the receive buffer (RXB) or by reception of the next data. If you want to find the details of an error,
therefore, ASIS must be read before reading RXB.
occur when the next data is received, and the receive error state will continue indefinitely.
time equivalent to two pulses of the clock that serves as the reference of the baud rate clock elapse
after the reception error occurs until the receive buffers (RXB, RXB2) are read. If the wait time
is not inserted, the reception completion interrupt occurs even when it is disabled.
The wait time equivalent to two pulses of the clock that serves as the reference of the baud rate
clock can be calculated by the following expression:
Wait time =
Remark f
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
Figure 16-9 Example of 3-Wire Serial I/O System Configuration
3-wire serial I/O
n : Value of baud rate generator control registers (BRGC, BRGC2) to select tap of 12-bit
XX
: Oscillation frequency
2
Master CPU
f
n+3
XX
prescaler (n = 0 to 11)
Port (Interrupt)
SCK
Port
SO
SI
*
SCK
SI
SO
Port
Interrupt (Port)
Slave CPU
415