UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 510

• Manufacturer Part Number: UPD784026
• Description: 16/8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Serial Clock
(SCK0)
Address
(A7 to A0)
Command
(C7 to C0)
Data
(D7 to D0)
* 1. For data transmission/reception, when the BUSY state is set, the transfer starts after transition to the READY state.
Signal Name
2. When WUP = 0, CSIIF is always set on the 8th rise of SCK0.
When WUP = 1, CSIIF is set on the 8th rise of SCK0 only when an address is received.
Outputting
Master/
Device
Master
Master
Master
slave
Synchronization
clock for output
of address/
command/data,
ACK signal,
synchronous
BUSY signal, etc.
Address/command/
data is transferred
in first 8 cycles.
8-bit data transferred
in synchronization
with SCK0 after REL
signal and CMD
signal output
8-bit data transferred
in synchronization
with SCK0 after CMD
signal only is output
without output of
REL signal
8-bit data transferred
in synchronization
with SCK0 without
output of either REL
signal or CMD signal
Definition
SCK0
SCK0
SCK0
SB0
SCK0
SB0
SB0
SB0
Table 17-1 Signals in SBI Mode (3/3)
1
REL CMD
CMD
2
2
Timing Chart
1
1
1
7
2
2
2
2
2
2
8
7
7
7
9
8
8
8
10
Output Conditions
(serial transfer
<2> Execution
= 0
and CRXE = 1
<3> Change of
CRXE bit from
0 to 1
<1> Execution
of instruction to
write data to SIO
when CTXE = 1
start directive)*
of instruction to
read data from
SIO when CTXE
1
CSIIF set (rise of
8th clock cycle)*
Effect on Flags
2
Timing of signal
output to serial
data bus
Address value of slave
device on serial bus
Directive or message
to slave device
Data to be processed
by slave or master
Meaning of Signal