UPD78F0138 NEC, UPD78F0138 Datasheet - Page 121

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

(2) Ring-OSC mode register (RCM)
Remarks 1. MCM0: Bit 0 of the main clock mode register (MCM)
Note The main clock mode register (MCM) is used to set the CPU clock (X1 input clock/Ring-OSC clock) (see
The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/KE1. Therefore, the relationship
between the CPU clock (f
This register sets the operation mode of Ring-OSC.
This register is valid when “Can be stopped by software” is set for Ring-OSC by a mask option, and the X1 input
clock or subsystem clock is selected as the CPU clock. If “Cannot be stopped” is selected for Ring-OSC by a
mask option, settings for this register are invalid.
RCM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
f
f
f
f
f
f
Address: FFA0H
X
X
X
X
X
XT
/2
/2
/2
/2
CPU Clock (f
/2
Symbol
2
3
4
RCM
Figure 5-4).
Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
2. f
3. f
4. f
5. f
Caution Make sure that the bit 1 (MCS) of the main clock mode register (MCM) is 1 before
X
R
XP
XT
: Main system clock oscillation frequency (X1 input clock oscillation frequency or Ring-OSC clock
: Ring-OSC clock oscillation frequency
CPU
: X1 input clock oscillation frequency
: Subsystem clock oscillation frequency
RSTOP
oscillation frequency)
)
7
0
0
1
After reset: 00H
0.2
0.4
0.8
1.6
3.2
setting RSTOP.
µ
µ
µ
µ
µ
Ring-OSC oscillating
Ring-OSC stopped
CPU
Figure 5-3. Format of Ring-OSC Mode Register (RCM)
(at 10 MHz Operation)
s
s
s
s
s
X1 Input Clock
) and minimum instruction execution time is as shown in the Table 5-2.
6
0
−
R/W
CHAPTER 5 CLOCK GENERATOR
Note
User’s Manual U16228EJ2V0UD
5
0
Minimum Instruction Execution Time: 2/f
8.3
16.6
33.2
66.4
132.8
(at 240 kHz (TYP.) Operation)
Ring-OSC oscillating/stopped
4
0
µ
s (TYP.)
µ
µ
µ
Ring-OSC Clock
s (TYP.)
s (TYP.)
s (TYP.)
µ
s (TYP.)
−
3
0
Note
2
0
122.1
CPU
(at 32.768 kHz Operation)
µ
Subsystem Clock
s
1
0
−
−
−
−
−
RSTOP
<0>
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