UPD78F0138 NEC, UPD78F0138 Datasheet - Page 131

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

Subsystem clock
(f
Ring-OSC clock
(f
XT
R
X1 input clock
(f
)
)
XP
Note Check using the oscillation stabilization time counter status register (OSTC).
(a) When the RESET signal is generated, bit 0 of the main clock mode register (MCM) is set to 0 and the Ring-
(b) After RESET release, the CPU clock can be switched from the Ring-OSC clock to the X1 input clock using bit
(c) Ring-OSC can be set to stopped/oscillating using the Ring-OSC mode register (RCM) when “Can be stopped
(d) When Ring-OSC is used as the CPU clock, the X1 input clock can be set to stopped/oscillating using the
(e) Select the X1 input clock oscillation stabilization time (2
)
CPU clock
RESET
OSC clock is set as the CPU clock. However, a clock is supplied to the CPU after 17 clocks of the Ring-OSC
clock have elapsed after RESET release (or clock supply to the CPU stops for 17 clocks). During the
RESET period, oscillation of the X1 input clock and Ring-OSC clock is stopped.
0 (MCM0) of the main clock mode register (MCM) after the X1 input clock oscillation stabilization time has
elapsed. At this time, check the oscillation stabilization time using the oscillation stabilization time counter
status register (OSTC) before switching the CPU clock. The CPU clock status can be checked using bit 1
(MCS) of MCM.
by software” is selected for the Ring-OSC by a mask option, if the X1 input or subsystem clock is used as the
CPU clock. Make sure that MCS is 1 at this time.
main OSC control register (MOC). Make sure that MCS is 0 at this time.
When the subsystem clock is used as the CPU clock, whether the X1 input clock stops or oscillates can be
set by the processor clock control register (PCC). In addition, HALT mode can be used during operation with
the subsystem clock, but STOP mode cannot be used (subsystem clock oscillation cannot be stopped by the
STOP instruction).
stabilization time select register (OSTS) when releasing STOP mode while X1 input clock is being used as
the CPU clock. In addition, when releasing STOP mode while RESET is released and Ring-OSC is being
used as the CPU clock, check the X1 input clock oscillation stabilization time using the oscillation
stabilization time counter status register (OSTC).
Operation
stopped: 17/f
Figure 5-12. Timing Diagram of CPU Default Start Using Ring-OSC
X1 oscillation stabilization time: 2
R
CHAPTER 5 CLOCK GENERATOR
User’s Manual U16228EJ2V0UD
Ring-OSC clock
11
/f
XP
to 2
16
/f
11
XP
/f
XP
Note
, 2
13
/f
XP
, 2
14
/f
XP
Switched by software
, 2
15
/f
XP
X1 input clock
, 2
16
/f
XP
) using the oscillation
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