UPD78F0138 NEC, UPD78F0138 Datasheet - Page 185

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

(6) Operation of OVF0n flag
(7) Conflicting operations
<1> The OFV0n flag is also set to 1 in the following case.
<2> Even if the OVF0n flag is cleared before the next count clock is counted (before TM0n becomes 0001H)
Conflict between the read period of the 16-bit timer capture/compare register (CR00n/CR01n) and capture trigger
input (CR00n/CR01n used as capture register)
Capture trigger input has priority. The data read from CR00n/CR01n is undefined.
When of the following modes: the mode in which clear & start occurs on a match between TM0n and
CR00n, the mode in which clear & start occurs on a TI0n valid edge, or the free-running mode, is selected
TM0n is counted up from FFFFH to 0000H.
after the occurrence of TM0n overflow, the OVF0n flag is re-set newly and clear is disabled.
Remark n = 0:
CR01n capture value
Capture read signal
TM0n count value
CR00n is set to FFFFH
n = 0, 1:
Count clock
Edge input
INTTM01n
Count clock
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01
INTTM00n
↓
↓
µ
µ
Figure 6-42. Capture Register Data Retention Timing
PD780131, 780132
PD780133, 780134, 78F0134, 780136, 780138, 78F0138
OVF0n
CR00n
TM0n
Figure 6-41. Operation Timing of OVF0n Flag
X
N
FFFEH
FFFFH
User’s Manual U16228EJ2V0UD
N + 1
FFFFH
Capture
N + 2
0000H
0001H
N + 2
M
Capture, but
read value is
not guaranteed
M + 1
M + 1
M + 2
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