UPD78F0138 NEC, UPD78F0138 Datasheet - Page 304
UPD78F0138
Manufacturer Part Number
UPD78F0138
Description
(UPD78xxxx) 8-Bit Single-Chip Microcontrollers
Manufacturer
NEC
Datasheet
1.UPD78F0138.pdf
(558 pages)
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(4) Clock selection register 6 (CKSR6)
304
Address: FF56H After reset: 00H R/W
Note To select the output of TM50 as the base clock, start the operation by setting 8-bit timer/event counter 50 so
Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the
Remarks 1. Figures in parentheses are for operation with f
Symbol
CKSR6
This register selects the base clock of serial interface UART6.
CKSR6 can be set by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation
that the duty is 50% of the output in the PWM mode (bit 6 (TMC506) of the TMC50 register = 1), and then
set TPS63, TPS62, TPS61, and TPS60 to 1, 0, 1, and 1, respectively. It is not necessary to enable the
TO50 pin as a timer output pin (bit 0 (TOE50) of the TMC register may be 0 or 1).
2. Make sure POWER6 = 0 when rewriting TPS63 to TPS60.
2. f
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
TPS63
Ring-OSC oscillator is divided and supplied as the count clock. If the base clock is the Ring-
OSC clock, the operation of serial interface UART6 is not guaranteed.
X
7
0
0
0
0
0
0
0
0
0
1
1
1
1
: X1 input clock oscillation frequency
Figure 14-8. Format of Clock Selection Register 6 (CKSR6)
TPS62
Other than above
6
0
0
0
0
0
1
1
1
1
0
0
0
0
CHAPTER 14 SERIAL INTERFACE UART6
TPS61
5
0
0
0
1
1
0
0
1
1
0
0
1
1
User’s Manual U16228EJ2V0UD
TPS60
4
0
0
1
0
1
0
1
0
1
0
1
0
1
X
f
f
f
f
f
f
f
f
f
f
f
TM50 output
Setting prohibited
= 10 MHz
X
X
X
X
X
X
X
X
X
X
X
/2 (5 MHz)
/2
/2
/2
/2
/2
/2
/2
/2
/2
(10 MHz)
TPS63
2
3
4
5
6
7
8
9
10
(2.5 MHz)
(1.25 MHz)
(625 kHz)
(312.5 kHz)
(156.25 kHz)
(78.13 kHz)
(39.06 kHz)
(19.53 kHz)
(9.77 kHz)
3
Note
Base clock (f
TPS62
2
XCLK6
) selection
TPS61
1
TPS60
0
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