UPD78F0138 NEC, UPD78F0138 Datasheet - Page 457

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

28.2 Operation List
8-bit data
transfer
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
3.
MOV
XCH
Mnemonic
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Except “r = A”
control register (PCC).
r, #byte
saddr, #byte
sfr, #byte
A, r
r, A
A, saddr
saddr, A
A, sfr
sfr, A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
[DE], A
A, [HL]
[HL], A
A, [HL + byte]
[HL + byte], A
A, [HL + B]
[HL + B], A
A, [HL + C]
[HL + C], A
A, r
A, saddr
A, sfr
A, !addr16
A, [DE]
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operands
CHAPTER 28 INSTRUCTION SET
Note 3
Note 3
Note 3
User’s Manual U16228EJ2V0UD
Bytes
2
3
3
1
1
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
1
1
1
1
2
2
3
1
1
2
2
2
Note 1
4
6
−
2
2
4
4
−
−
8
8
−
−
−
4
4
4
4
8
8
6
6
6
6
2
4
−
8
4
4
8
8
8
Clocks
10 + n + m A ↔ (addr16)
10 + n + m A ↔ (HL + byte)
10 + n + m A ↔ (HL + B)
10 + n + m A ↔ (HL + C)
6 + n + m A ↔ (DE)
6 + n + m A ↔ (HL)
Note 2
9 + m
5 + m
5 + m
9 + m
7 + m
7 + m
9 + n
5 + n
5 + n
9 + n
7 + n
7 + n
−
7
7
−
−
5
5
5
7
5
5
−
6
5
6
r ← byte
(saddr) ← byte
sfr ← byte
A ← r
r ← A
A ← (saddr)
(saddr) ← A
A ← sfr
sfr ← A
A ← (addr16)
(addr16) ← A
PSW ← byte
A ← PSW
PSW ← A
A ← (DE)
(DE) ← A
A ← (HL)
(HL) ← A
A ← (HL + byte)
(HL + byte) ← A
A ← (HL + B)
(HL + B) ← A
A ← (HL + C)
(HL + C) ← A
A ↔ r
A ↔ (saddr)
A ↔ (sfr)
CPU
) selected by the processor clock
Operation
Z AC CY
×
×
Flag
×
×
457
×
×