UPD78F0138 NEC, UPD78F0138 Datasheet - Page 557

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

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Modification of Notes 4 and 5 in Figure 5-13 Status Transition Diagram (2)
Modification of Note 4 and illustration in Figure 5-13 Status Transition Diagram (4)
Modification of Table 5-3 Relationship Between Operation Clocks in Each Operation Status
Modification of Note in Figure 5-14 Switching from Ring-OSC Clock to X1 Input Clock (Flowchart)
Addition of Note to Figure 5-16 Switching from X1 Input Clock to Subsystem Clock (Flowchart)
Revision of CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Revision of CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
Revision of CHAPTER 8 8-BIT TIMERS H0 AND H1
Modification of Figure 9-1 Block Diagram of Watch Timer
Addition of Figure 9-4 Example of Generation of Watch Timer Interrupt Request (INTWT) (When
Interrupt Period = 0.5 s)
Modification of Figure 11-1 Block Diagram of Clock Output/Buzzer Output Controller
Revision of CHAPTER 12 A/D CONVERTER
Revision of CHAPTER 13 SERIAL INTERFACE UART0
Revision of CHAPTER 14 SERIAL INTERFACE UART6
Revision of CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11
Revision of CHAPTER 16 MULTIPLIER/DIVIDER
Addition of Note to INTVLI, POC, and LVI in Table 17-1 Interrupt Source List
Addition of Note 2 to Table 17-2 Flags Corresponding to Interrupt Request Sources
Addition of Caution 2 to Figure 17-2 Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H)
Addition of Caution to Table 17-3 Ports Corresponding to EGPn and EGNn
Addition of software interrupt request item to Table 17-5 Relationship Between Interrupt Requests
Enabled for Multiple Interrupt Servicing During Interrupt Servicing
Modification of Figure 18-1 Block Diagram of Key Interrupt
Modification of Table 19-1 Relationship Between HALT Mode, STOP Mode, and Clock in old edition to
Table 19-1 Relationship Between Operation Clocks in Each Operation Status
Addition of Cautions 2 and 3 to Figure 19-1 Format of Oscillation Stabilization Time Counter Status
Register (OSTC)
Modification of Table 19-2 Operating Statuses in HALT Mode
Addition of (3) When subsystem clock is used as CPU clock to Figure 19-4 HALT Mode Release by
RESET Input
Modification of the following items in Table 19-4 Operating Statuses in STOP Mode
• 8-bit timer H0
• Serial interfaces UART0 and UART6
Modification of Figure 20-1 Block Diagram of Reset Function to Figure 20-4 Timing of Reset in STOP
Mode by RESET Input
Modification of Figure 21-1 Block Diagram of Clock Monitor
Addition of normal operation mode to Table 21-2 Operation Status of Clock Monitor (When CLME = 1)
Addition of (6) Clock monitor status after X1 input clock oscillation is stopped by software and (7)
Clock monitor status after Ring-OSC clock oscillation is stopped by software to Figure 21-3 Timing of
Clock Monitor
APPENDIX D REVISION HISTORY
User’s Manual U16228EJ2V0UD
Description
(2/3)
557