UPD78F0138 NEC, UPD78F0138 Datasheet - Page 291

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

(4) Permissible baud rate range during reception
The permissible error from the baud rate at the transmission destination during reception is shown below.
Caution Make sure that the baud rate error during reception is within the permissible error range, by
As shown in Figure 13-12, the latch timing of the receive data is determined by the counter set by baud rate
generator control register 0 (BRGC0) after the start bit has been detected. If the last data (stop bit) meets this
latch timing, the data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows.
Maximum permissible
Minimum permissible
FL = (Brate)
Data frame length
Brate: Baud rate of UART0
k:
FL:
Margin of latch timing: 2 clocks
data frame length
data frame length
using the calculation expression shown below.
of UART0
Set value of BRGC0
1-bit data length
−
1
Figure 13-12. Permissible Baud Rate Range During Reception
Latch timing
Start bit
Start bit
Start bit
CHAPTER 13 SERIAL INTERFACE UART0
User’s Manual U16228EJ2V0UD
Bit 0
Bit 0
FL
Bit 0
Bit 1
Bit 1
Bit 1
1 data frame (11
FLmin
FLmax
Bit 7
Bit 7
FL)
Bit 7
Parity bit
Parity bit
Parity bit
Stop bit
Stop bit
Stop bit
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