UPD78F0138 NEC, UPD78F0138 Datasheet - Page 130

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UPD78F0138

Manufacturer Part Number
UPD78F0138
Description
(UPD78xxxx) 8-Bit Single-Chip Microcontrollers
Manufacturer
NEC
Datasheet

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5.5 Clock Generator Operation
mode.
78K0/KE1, thus enabling the following.
(1) Enhancement of security function
(2) Improvement of performance
130
The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby
• X1 input clock f
• Ring-OSC clock f
• Subsystem clock f
• CPU clock f
• Clock to peripheral hardware
The CPU starts operation when the on-chip Ring-OSC oscillator starts outputting after reset release in the
When the X1 input clock is set as the CPU clock by the default setting, the device cannot operate if the X1 input
clock is damaged or badly connected and therefore does not operate after reset is released. However, the start
clock of the CPU is the on-chip Ring-OSC clock, so the device can be started by the Ring-OSC clock after reset
release by the clock monitor (detection of X1 input clock stop). Consequently, the system can be safely shut
down by performing a minimum operation, such as acknowledging a reset source by software or performing
safety processing when there is a malfunction.
Because the CPU can be started without waiting for the X1 input clock oscillation stabilization time, the total
performance can be improved.
A timing diagram of the CPU default start using Ring-OSC is shown in Figure 5-12.
CPU
XP
R
XT
CHAPTER 5 CLOCK GENERATOR
User’s Manual U16228EJ2V0UD

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