UPD78F0138 NEC, UPD78F0138 Datasheet - Page 406

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

automatically starts at the end of the X1 input clock oscillation stabilization time. Monitoring is stopped in STOP mode
and during the oscillation stabilization time.
clock is stopped, monitoring automatically starts at the end of the X1 input clock oscillation stabilization time.
Monitoring is stopped when oscillation of the X1 input clock is stopped and during the oscillation stabilization time.
406
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before or while oscillation of the X1 input
Note The register that controls oscillation of the X1 input clock differs depending on the type of the clock supplied
Clock monitor status
Clock monitor status
Ring-OSC clock
Ring-OSC clock
(CLME = 1 is set when CPU clock operates on Ring-OSC clock and before entering STOP mode)
CPU operation
CPU operation
X1 input clock
X1 input clock
to the CPU.
(CPU clock)
• When CPU operates on Ring-OSC clock:
• When CPU operates on subsystem clock: Controlled by bit 7 (MCC) of the processor clock control
MSTOP or
MCC
CLME
CLME
(6) Clock monitor status after X1 input clock oscillation is stopped by software
Note
operation
Normal
Monitoring
Monitoring
(5) Clock monitor status after STOP mode is released
Figure 21-3. Timing of Clock Monitor (3/4)
Oscillation
Monitoring
Monitoring
Oscillation
stopped
stopped
stopped
stopped
STOP
CHAPTER 21 CLOCK MONITOR
Normal operation (Ring-OSC clock or subsystem clock
User’s Manual U16228EJ2V0UD
Oscillation stabilization time
Oscillation stabilization time
(time set by OSTS register)
(time set by OSTS register)
Clock supply
Monitoring stopped
Monitoring stopped
17 clocks
stopped
Controlled by bit 7 (MSTOP) of the main OSC control
register (MOC)
register (PCC)
Normal operation
Note
Monitoring
)
Monitoring