UPD78F0138 NEC, UPD78F0138 Datasheet - Page 402

• Manufacturer Part Number: UPD78F0138
• Description: (UPD78xxxx) 8-Bit Single-Chip Microcontrollers
• Manufacturer: NEC

21.3 Registers Controlling Clock Monitor
(1) Clock monitor mode register (CLM)
402
The clock monitor is controlled by the clock monitor mode register (CLM).
Cautions 1. Once bit 0 (CLME) is set to 1, it cannot be cleared to 0 except by RESET input or the internal
This register sets the operation mode of the clock monitor.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Symbol
Address: FFA9H
CLM
2. If the reset signal is generated by the clock monitor, CLME is cleared to 0 and bit 1 (CLMRF)
CLME
reset signal.
of the reset control flag register (RESF) is set to 1.
7
0
0
1
After reset: 00H
Figure 21-2. Format of Clock Monitor Mode Register (CLM)
Disables clock monitor operation
Enables clock monitor operation
6
0
R/W
CHAPTER 21 CLOCK MONITOR
5
0
User’s Manual U16228EJ2V0UD
Enables/disables clock monitor operation
4
0
3
0
2
0
1
0
CLME
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