pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 124

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

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After finding the data field, the controller transfers data
bytes from the disk drive to the host until the bytes-per-sec-
tor count has been reached, or until the host terminates the
operation by issuing the Terminal Count (TC) signal, reach-
ing the end of the track or reporting an overrun.
See also Section 5.4 "THE PHASES OF FDC COM-
MANDS" on page 104.
The controller then generates a Cyclic Redundancy Check
(CRC) value for the sector and compares the result with the
CRC value at the end of the data field.
After reading the sector, the controller reads the next logical
sector unless one or more of the following termination con-
ditions occurs:
If the Multi-Track (MT) bit was set in the opcode command
byte, and the last sector of side 0 has been transferred, the
controller continues with side 1.
Result Phase
Control
Skip
(SK)
7
The DMA controller asserted the Terminal Count (TC)
signal to indicate that the operation terminated. The In-
terrupt Code (IC) bits (bits 7,6) in ST0 are set to normal
termination (00). See “Bits 7,6 - Interrupt Code (IC)” on
page 107.
The last sector address (of side 1, if the Multi-Track en-
able bit (MT) was set to 1) was equal to the End of Track
sector number. The End of Track bit (bit 7) in ST1 is set.
The IC bits in ST0 are set to abnormal termination (01).
This is the expected condition during non-DMA transfers.
Overrun error. The Overrun bit (bit 4) in ST1 is set. The
Interrupt Code (IC) bits (bits 7,6) in ST0 are set to abnor-
mal termination (01). If the microprocessor cannot ser-
vice a transfer request in time, the last correctly read
byte is transferred.
CRC error. CRC Error bit (bit 5) in ST1 and CRC Error in
Data Field bit (bit 5) in ST2, are set. The Interrupt Code (IC)
bits (bits 7,6) in ST0 are set to abnormal termination (01).
TABLE 5-17. Skip Control Effect on READ DATA
0
0
1
1
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
6
Deleted
Deleted
Normal
Normal
Type
Data
5
Sector
Read?
Command
Y
Y
Y
N
4
Mark Bit 6
Control
of ST2
3
0
1
0
1
2
Sector Skipped
Sectors Read
Termination
Termination
No More
Normal
Normal
Result
1
0
124
Upon terminating the execution phase of the READ DATA
command, the controller asserts IRQ6, indicating the begin-
ning of the result phase. The microprocessor must then
read the result bytes from the FIFO.
The values that are read back in the result bytes are shown
in TABLE 5-18 "Result Phase Termination Values with No
Error" on page 125. If an error occurs, the result bytes indi-
cate the sector read when the error occurred.
5.7.11 The READ DELETED DATA Command
The READ DELETED DATA command reads logical sec-
tors containing a Address Mark (AM) for deleted data from
the selected drive and makes the data available to the host
microprocessor.
This command is like the READ DATA command, except for the
setting of the Control Mark bit (bit 6) in ST2 and the skipping of
sectors. See description of execution phase. See READ DATA
command for a description of the command bytes.
Command Phase
Execution Phase
Data read from disk drive is transferred to the system in
DMA or non-DMA modes. See Section 5.4.2 "Execution
Phase" on page 104.
See TABLE 5-18 "Result Phase Termination Values with
No Error" for the state of the result bytes when the com-
mand terminates normally. The effect of Skip Control (SK)
on the READ DELETED DATA command is summarized in
TABLE 5-19 "SK Effect on READ DELETED DATA Com-
mand".
IPS
MT
7
7
MFM
X
6
6
End of Track (EOT) Sector Number
Bytes Between Sectors - Gap 3
SK
X
Data Length (Obsolete)
5
5
Bytes-Per-Sector Code
Bytes-Per-Sector Code
Sector Number
Sector Number
Track Number
Head Number
Track Number
Head Number
X
4
4
0
X
3
3
1
HD
2
2
1
DS1
1
1
0
DS0
0
0
0