pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 168

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

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Bits 7-4- Reserved
Interrupt Enable Register (IER), in the Extended Modes
of UART, Sharp-IR and SIR
Figure 7-6 shows the bitmap of the Interrupt Enable Regis-
ter in these modes.
FIGURE 7-6. IER Register Bitmap, Extended Modes of
Bit 0 - Receiver High-Data-Level Interrupt Enable
(RXHDL_IE)
Bit 1 - Transmitter Low-Data-Level Interrupt Enable
(TXLDL_IE)
Bit 2 - Link Status Interrupt Enable (LS_IE)
Bit 3 - Modem Status Interrupt Enable (MS_IE)
0
7
0 - Disable Modem Status Interrupts (MS_EV) (De-
1: Enable Modem Status Interrupts (MS_EV).
These bits are reserved.
Setting this bit enables interrupts when the RX_FIFO is
equal to or above the RX_FIFO threshold level, or an
RX_FIFO time out occurs.
0: Disable Receiver Data Ready interrupt. (Default)
1: Enable Receiver Data Ready interrupt.
Setting this bit enables interrupts when the TX_FIFO is
below the threshold level or the Transmitter Holding
Register is empty.
0: Disable Transmitter Low-Data-Level Interrupts (De-
1: Enable Transmitter Low-Data-Level Interrupts.
Setting this bit enables interrupts on Link Status events.
0: Disable Link Status Interrupts (LS_EV) (Default)
1: Enable Link Status Interrupts (LS_EV).
Setting this bit enables the interrupts on Modem Status
events.
0: Disable Modem Status Interrupts (MS_EV) (De-
1: Enable Modem Status Interrupts (MS_EV).
Reserved
0
Extended Mode of UART, Sharp-IR and SIR
6
fault).
fault).
fault)
Reserved
0
5
0
TXEMP_IE
4
DMA_IE
0
3
UART and Sharp-IR
0
MS_IE
2
LS_IE
0
1
TXLDL_IE
0
0
RXHDL_IE
Reset
Required
Enhanced Serial Port with IR - UART2 (Logical Device 5)
Interrupt Enable
Register (IER)
Offset 01h
Bank 0,
168
Bit 4 - DMA Interrupt Enable (DMA_IE)
Bit 5 - Transmitter Empty Interrupt Enable (TXEMP_IE)
Bits 7,6 - Reserved
Interrupt Enable Register (IER), Consumer-IR Mode
Figure 7-7 shows the bitmap of the Interrupt Enable Regis-
ter (IER) in this mode.
FIGURE 7-7. IER Register Bitmap, Consumer-IR Mode
Bit 1-0 -
Bit 2 - Link Status Interrupt Enable (LS_IE) or TX_FIFO
Underrun Interrupt Enable (TXUR_IE)
Bit 7-3 -
7.11.3 Event Identification Register (EIR)
The Event Identification Register (EIR) and the FIFO
Control Register (FCR) (see next register description)
share the same address. The EIR is accessed during CPU
read cycles while the FCR is accessed during CPU write cy-
0
7
Setting this bit enables the interrupt on terminal count
when the DMA is enabled.
0: Disable DMA terminal count interrupt (Default)
1: Enable DMA terminal count interrupt.
Setting this bit enables interrupt generation if the trans-
mitter and TX_FIFO become empty.
0: Disable Transmitter Empty interrupts (Default)
1: Enable Transmitter Empty interrupts.
Reserved.
Same as in the Extended Modes of UART and Sharp-IR
(See previous sections).
On reception, Setting this bit enables Link Status Interrupts.
On transmission, Setting this bit enables TX_FIFO un-
derrun interrupts.
0: Disable Link Status and TX_FIFO underrun inter-
1: Enable Link Status and TX_FIFO underrun interrupts.
Same as in the Extended Modes of UART and Sharp-IR
(See the section “Interrupt Enable Register (IER), in the
Extended Modes of UART, Sharp-IR and SIR” on page
168).
Reserved
0
6
rupts (Default)
Reserved
0
5
TXEMP_IE
0
4
DMA_IE
0
3
MS_IE
0
2
LS_IE or TXUR_IE
0
1
Consumer-IR Mode
0
TXLDL_IE
0
Reset
Required
RXHDL_IE
Interrupt Enable
Register (IER)
Offset 01h
Bank 0,