pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 65

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

4.4.2
Power Up
When power is first applied to the RTC, (referred to as first
Power on) the APC registers are initialized to the default
values defined in the register descriptions. (See TABLE
4-22 "Bank 2 Registers - APC Memory Bank" on page 90).
This situation is defined by the appearance of V
with no previous power.
The APC powers up when the RTC supply is applied from
any source and is always in an active state. The RTC may
be powered up, but inactive; this occurs if bit 0 of the regis-
ter at index 30h (see Section 2.3 "THE CONFIGURATION
REGISTERS" on page 29) of this logical device is not set.
In this situation, the APC registers are not accessible, since
they are only accessed via the RTC. This is also true of the
general-purpose battery-backed RAM.
Power Off Request (POR)
The APC allows a maskable or non-maskable interrupt on
the POR pin. This interrupt enables the user to perform an
orderly exit procedure, automatically performing house-
keeping functions such as file backups, printout completion
and communications terminations, before powering down.
See FIGURE 4-12 "POR, SCI and ONCTL Generation" on
page 66.
The POR signal can be asserted by the following events:
An event will assert POR, only if its corresponding status
and enable bits are set.
Each of the events (PME1 to P12, in the list above) has a
corresponding status bit in the GP1_STS0 register. The
events can be enabled via two registers. When bit 0 of the
PM1_CNT_LOW register is 0, the events can be enabled
via their corresponding bit in the GP1_EN0 register. A bit in
the GP2_EN0 register can always enable its corresponding
event (All registers referred to in this paragraph are in the
ACPI Fixed registers).
The PC87317 also supports the SMI Command of the AC-
PI. Thus, when bit 5 (status) and bit 6 (enable) of the ACPI
Support register are '1', POR is asserted (see Power Man-
agement registers, Logical Device 8). This is the SMI Com-
mand event. It is initiated by the ACPI OS that writes to the
SMI Command register.
Power Button (Switch-Off Event).
ACPI Global Lock Release.
Sleep Enable.
SMI Command.
PME1 Event.
PME2 Event.
IRRX1 Event.
IRRX2 Event.
GPIO12 Event.
GPIO13 Event.
GPIO10 Event.
P12 Event.
Entering Power States
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
BAT
or V
CCH
65
The PC87317 supports the Global Lock mechanism of the
ACPI. Thus, when bit 2 (status) and bit 3 (enable) of the
ACPI Support register are set to 1, POR is asserted (see
Power Management registers, Logical Device 8). This is the
ACPI Global Lock Release event. It is initiated by the ACPI
OS that writes a 1 to the ACPI Global Lock Release bit in
the PM1_CNT_LOW register (see Fixed ACPI registers).
The system can enter suspend modes via software emula-
tion. When bit 0 (status) and bit 1 (enable) of the ACPI Sup-
port register are set to 1, POR is asserted (see Power
Management registers, Logical Device 8). This is the Sleep
Enable event. It is initiated by the ACPI OS that writes a 1
to the Sleep Enable bit in the PM1_CNT_HIGH register (see
Fixed ACPI registers).
The Power Button (Switch-Off Event) can assert the POR
pin, only when the SCI/POR bit is 0 (see PM1_CNT_LOW
register in the ACPI Fixed registers). It will assert the POR
pin, when a Switch-Off event is detected, regardless of the
Power Button Enable bit (see PM1_EN_HIGH register in
the ACPI Fixed registers).
When POR is in level mode (bit 2 of APCR1 register is 1), it
is asserted until the corresponding event’s status bit or en-
able bit is cleared. The exception to this is the Switch-Off
event. For that event, POR will be deasserted by the Level
POR Clear Command bit (bit 3 of the APCR1 register). Note
that if level events are configured, the POR must be config-
ured to level mode. When any of the following events is en-
abled, POR must also be configured to level mode:
Upon Master Reset, the POR signal is in TRI-STATE.
Power Failure
The APC is in a Power Failure state when it is powered by
V
Upon entering a Power Failure state, the following occurs:
The nature of the system recovery after power failure is set
by bits 6 and 7 of the APCR6 control register (See Section
4.5.13 "APC Control Register 6 (APCR6)" on page 75).
In all cases, the system can be switched on manually after
Three selectable automatic options exist:
BAT
Writes to the SMI Command register.
Write 1 to the ACPI Global Lock Release bit of the
PM1_CNT_LOW register
Write
PM1_CNT_HIGH register.
All APC inputs are masked (high).
These signals remain masked until one second after
exit from the Power Failure state, i.e., one second after
switching from V
The ONCTL pin state is internally saved, and ONCTL is
forced inactive. System Recovery after Power Failure
power returns.
the system response is controlled by the MOAP bit
the system remains inactive after power returns until
an enabled “wake-up” event occurs
the system is awakened when power returns by a new
enabled wake-up event, or by an enabled “match
event” that occurred while power was down.
, without V
1
CCH
to
.
BAT
the
to V
Sleep
CCH
.
Enable
bit
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