pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 206

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

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Bit 0 - RX_FIFO Time-Out (RXF_TOUT)
Bits 7 - 1 -Reserved
8.6 BANK 1 – THE LEGACY BAUD GENERATOR
This register bank contains two registers as the Baud Gen-
erator Divisor Port, and a bank select register.
The Legacy Baud Generator Divisor (LBGD) port provides
an alternate path to the Baud Divisor Generator register.
This bank is implemented to maintain compatibility with
16550 standard and to support existing legacy software
packages. In case of using legacy software, the addresses
0 and 1 are shared with the data ports RXD/TXD (see page
197). The selection between them is controlled by the value
of the BKSE bit (LCR bit 7 page 201).
In addition, a fallback mechanism maintains this compatibil-
ity by forcing the UART to revert to 16550 mode if 16550
software addresses the module after a different mode was
set. Since setting the baud rate divisor values is a neces-
sary initialization of the 16550, setting the divisor values in
bank 1 forces the UART to enter 16550 mode. (This is
called fallback.)
To enable other modes to program their desired baud rates
without activating this fallback mechanism, the baud rate di-
visor register in bank 2 should be used.
8.6.1
The programmable baud rates in the Non-Extended mode
are achieved by dividing a 24 MHz clock by a prescale value
of 13, 1.625 or 1. This prescale value is selected by the
PRESL field of EXCR2 (see page 209). This clock is subdi-
vided by the two baud rate generator divisor buffers, which
output a clock at 16 times the desired baud rate (this clock is
the BOUT clock). This clock is used by I/O circuitry, and after
a last division by 16 produces the output baud rate.
Divisor values between 1 and 2
forbidden). The baud rate generator divisor must be loaded
during initialization to ensure proper operation of the baud
rate generator. Upon loading either part of it, the baud rate
generator counter is immediately loaded. Table 8-12 on
page 208 shows typical baud divisors. After reset the divisor
register contents are indeterminate.
04h - 07h
Offset
This bit is read only and set to 1 when an RX_FIFO tim-
eout occurs. It is cleared when a character is read from
the RX_FIFO.
Read/Write 0.
00h
01h
02h
03h
DIVISOR PORTS
Legacy Baud Generator Divisor Ports (LBGD(L)
and LBGD(H)),
TABLE 8-9. Bank 1 Register Set
LBGD(H)
Register
LBGD(L)
Name
LCR/
BSR
Legacy Baud Generator
Legacy Baud Generator
Divisor Port (High Byte)
Divisor Port (Low Byte)
Bank Select Register
Reserved
Reserved
16
-1 can be used. (Zero is
Line Control /
Description
Enhanced Serial Port - UART1 (Logical Device 6)
206
Any access to the LBGD(L) or LBGD(H) ports causes a re-
set to the default Non-Extended mode, i.e., 16550 mode
(See “AUTOMATIC FALLBACK TO A NON-EXTENDED
UART MODE” on page 197).To access a Baud Generator
Divisor when in the Extended mode, use the port pair in
bank 2 (BGD on page 207).
Table 8-10 shows the bits which are cleared when Fallback
occurs during Extended or Non-Extended modes.
If the UART is in Non-Extended mode and the LOCK bit is
1, the content of the divisor (BGD) ports will not be affected
and no other action is taken.
When programming the baud rate, the new divisor is loaded
upon writing into LBGD(L) and LBGD(H). After reset, the
contents of these registers are indeterminate.
Divisor values between 1 and 2
forbidden.) Table 8-12 shows typical baud rate divisors.
.
.
Register
EXCR1
EXCR2
7
7
MCR
6
6
FIGURE 8-19. LBGD(H) Register Bitmap
FIGURE 8-18. LBGD(L) Register Bitmap
TABLE 8-10. Bits Cleared On Fallback
5
5
LOCK = x
Extended
0, 5 and 7
UART Mode & LOCK bit before Fallback
4
4
Mode
2 to 7
0 to 5
3
3
Most Significant Byte
2
2
Least Significant Byte
Legacy Baud Generator Divisor
Legacy Baud Generator Divisor
Non-Extended
1
1
of Baud Generator
LOCK = 0
of Baud Generator
5 and 7
0
0
Mode
0 to 5
none
Reset
Required
Reset
Required
16
-1 can be used. (Zero is
High Byte port
Non-Extended
Low Byte port
LOCK = 1
(LBGD(L))
Offset 00h
Offset 01h
(LBGD(H))
Mode
none
none
none
Bank 1,
Bank 1,