pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 44

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

www.national.com
2.10.8 Reserved
Attempts to access this register produce undefined results.
2.10.9 CS2 Base Address MSB Register
This read/write register is reset by hardware to 00h. It func-
tions like the Plug and Play ISA base address register at in-
dex 60h. See TABLE 2-7 "Plug and Play (PnP) I/O Space
Configuration Registers" on page 31.
2.10.10 CS2 Base Address LSB Register
This read/write register is reset by hardware to 00h. It func-
tions like the Plug and Play ISA base address register at in-
dex 61h. See TABLE 2-7 "Plug and Play (PnP) I/O Space
Configuration Registers" on page 31.
2.10.11 CS2 Configuration Register
This read/write register is reset by hardware to 00h. It func-
tions like the CS0 Configuration register.
2.10.12 Reserved, Second Level Indexes 0Bh-0Fh
Attempts to access these registers produce undefined re-
sults.
2.10.13 Not Accessible, Second Level Indexes 10h-FFh
Not accessible because bits 7-4 of the Index register are 0.
FIGURE 2-16. SuperI/O CS1 Configuration Register
FIGURE 2-17. SuperI/O CS2 Configuration Register
0
0
7
7
0
0
Mask Address Pins A11
Mask Address Pins A11
6
6
Unaffected by RD/WR
Unaffected by RD/WR
0
0
5
5
Assert Chip Select Signal on Read
Assert Chip Select Signal on Read
0
0
4
4
Assert Chip Select Signal on Write
Assert Chip Select Signal on Write
0
0
3
3
Mask Address Pin A3
Mask Address Pin A3
0
0
2
2
Mask Address Pin A2
Mask Address Pin A2
0
0
1
1
Bitmap
Bitmap
Mask Address Pin A1
Mask Address Pin A1
0
0
0
0
Reset
Required
Reset
Required
Mask Address Pin A0
Mask Address Pin A0
CS1 Configuration
CS2 Configuration
Second Level
Second Level
Index 0Ah
Index 06h
Register,
Register,
Configuration
44
2.11 CONFIGURATION REGISTER BITMAPS
0
7
1
1
1
1
0
7
7
7
GPIO Bank Select
0
6
1
1
1
1
0
6
6
6
GPIO17 or WDO Pin Select
General Purpose Scratch Bits
0
5
0
0
0
0
0
5
5
5
GPIO20 or IRSL1 Pin Select
0
Lock Scratch Bit
4
1
1
1
1
x
4
4
4
Chip ID
0
X-Bus Data Buffer (XDB) Select
0
0
1
1
0
3
3
3
3
GPIO21, IRSL2, ID2 or ISL0 Pin Select
UART2 or GPIO30-36 Select
0
0
0
1
1
1
2
2
2
2
Chip ID
PC-AT or PS/2 Drive Mode Select
GPIO22 or POR Select
x
0
0
1
1
x
1
1
1
1
CSOUT or CS0 Select
x
0
0
1
1
0
0
0
0
0
Revision ID
SuperI/O Configuration 2
Reset
Required
BADDR1 and BADDR0
SuperI/O Configuration 1
Reset
Required
Reset
Required
Reset
Required
ZWS Enable
Register (SIOC2),
Register (SIOC1),
SID (In PC87317)
SID (In PC97317)
Index 22h
Index 21h
Index 20h
Index 20h
Register,
Register,