pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 79

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

Bit 7 - Wake Status (WAK_STS)
4.6.3
Reserved bits are read-only. Read returns 0.
Bit 0 - Timer Enable (TMR_EN)
Bits 4-1 - Reserved
Bit 5 - Global Lock Enable (GBL_EN)
Bits 7-6 - Reserved
7
0
This bit is set to 1, when the system is in the suspended
state and an enabled Power Management event occurs.
Exception to this is the Switch-Off event that can set this
bit to '1', regardless of the Power Button Enable bit. Un-
like the other status bits of this register, reset overrides
set.
Suspend state starts when Sleep Enable bit (of
PM1_CNT_HIGH register) is written with a 1.
Suspend
PM1_STS_HIGH,
PM1_CNT_LOW,
GP1_EN0,
PM1_TMR_MID, PM1_TMR_HIGH or PM1_TMR_EXT is
accessed while Wake Status bit (of PM1_STS_HIGH reg-
ister) is set. It ends on first access to any of these registers.
Power Management events that affect this bit: RTC
Alarm, Power Button, PME1, PME2, IRRX1, IRRX2,
GPIO10, GPIO12, GPIO13, P12 (enabled by the
GP1_EN0 register).
This pin is reset to 0 upon Master Reset.
0: Timer Status bit is ignored (bit 0 of the
PM1_STS_LOW register)
1: Activate the SCI signal, when the Timer Status bit
This pin is reset to 0 upon Master Reset.
0: Global Lock Status bit is ignored (bit 5 of the
1: Activate the SCI signal, when the Global Lock Sta-
FIGURE 4-34. PM1_EN_LOW Register Bitmap
0
6
is set to 1.
PM1_STS_LOW register)
tus bit is set to 1.
Power Management 1 Enable Low Byte
Register (PM1_EN_LOW)
Reserved
0
5
GBL_EN
0
4
state
0
3
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
0
2
GP2_EN0,
Reserved
PM1_EN_LOW,
ends
0
1
PM1_CNT_HIGH,
Power Management 1 Enable
0
0
Power-Up
Reset
Required
TMR_EN
when
Low Byte Register
(PM1_EN_LOW)
PM1_TMR_LOW,
PM1_STS_LOW,
PM1_EN_HIGH,
GP1_STS0,
Offset 02h
79
4.6.4
Reserved bits are read-only, and will always return 0.
Bit 0 - Power Button Enable (PWRBTN_EN)
Bit 1 - Reserved
Bit 2 - Real Time Clock Alarm Enable (RTC_EN)
Bits 7-3 - Reserved
7
0
This pin is reset to 0 upon Master Reset.
0: Power Button Status bit is ignored (bit 0 of
1: Activate the SCI pin when the Power Button Status
0: Real Time Clock Alarm status bit is ignored (bit 2 of
1: Activate the ONCTL pin and the SCI signal when
FIGURE 4-35. PM1_EN_HIGH Register Bitmap
6
0
PM1_STS_HIGH)
bit is set to 1.
PM1_STS_HIGH)
the Real Time Clock Status bit is set to 1.
Power Management 1 Enable High Byte
Register (PM1_EN_HIGH)
0
5
0
4
Reserved
0
3
0
2
0
RTC_EN
1
Power Management 1 Enable
Reserved
0
0
PWRBTN_EN
Power-Up
Reset
Required
High Byte Register
(PM1_EN_HIGH)
Offset 03h
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