pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 78

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

www.national.com
4.6 ACPI FIXED REGISTERS
The APCI fixed registers are divided into four groups:
These registers, their base address locations and their ad-
dress offsets are listed in TABLE 4-5 "ACPI Fixed Register
List." on page 61. These registers are accessed using their
base address and the offset from the base address.
The APCI Fixed registers are reset to 0 upon first Power Up,
and are unaffected by Master Reset (unless specifically
mentioned otherwise).
Access to these registers is disabled by default and must be
enabled via FER2 (see Section 10.2.4 on page 219). The
access is not controlled by the Active register (Index 30h) of
Logical Device 2 (RTC/APC) or by the Active register (Index
30h) of Logical Device 8 (Power Management).
PM1 EVENT REGISTERS
4.6.1
All implemented bits are “sticky” bits: they are set to 1 by a
hardware event, and are reset to 0 only by software writing
a 1 to the bit location. (Set overrides reset in the event of
conflict).
Reserved bits are read-only, and will always return 0.
Bit 0 - Timer Status (TMR_STS)
Bits 4-1 - Reserved
Bit 5 - Global Lock Status (GBL_STS)
Bits 7-6 - Reserved
7
0
PM1 Event registers
PM1 Control registers
PM TImer registers
General Purpose Event registers
This bit is set to 1 when the most significant bit of the
Power
PM1_TMR_HIGH) changes from low to high or from
high to low.
This bit is set to 1 when a 1 is written to the BIOS Global
Lock Release bit (See ACPI Support register, Power
Management registers, in Logical device 8).
FIGURE 4-32. PM1_STS_LOW Register Bitmap
0
6
Power Management 1 Status Low Byte Register
(PM1_STS_LOW)
Reserved
0
5
0
4
GBL_STS
Management
0
3
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
0
2
Reserved
0
1
Power Management 1 Status
0
0
Timer
Power-Up
Reset
Required
TMR_STS
(bit
Low Byte Register
(PM1_STS_LOW)
23
Offset 00h
-
See
78
POWER MANAGEMENT REGISTERS
4.6.2
All implemented bits are “sticky” bits: they are set to 1 by a
hardware event, and are reset to 0 only by software writing
a 1 to the bit location.Reserved bits are read-only, and will
always return 0. Set overrides reset.
Bit 0 - Power Button Status (PWRBTN_STS)
Bit 1- Reserved
Bit 2 - Real Time Clock Status (RTC_STS)
Bit 3 - Power Button Override Status
(PWRBTNOR_STS)
Bit 6-4 - Reserved
7
0
This bit is set to 1 when a high to low transition is detect-
ed on the SWITCH, regardless of the Power Button En-
able bit (bit 0 of the PM1_EN_HIGH register). This bit
may be cleared to 0 by either software (as described
above) or by hardware, when the SWITCH input signal
is 0 for over 3.95 or 4 seconds (as selected by bit 3 of
APCR7). A high to low transition on the SWITCH input
pin that occurs while the Power Button Status bit is be-
ing cleared by software may be lost. The SWITCH state
is detected after the debouncer.
This bit is set to 1 when the real time clock detects an
alarm condition (even if bit 5 of the RTC Control Regis-
ter C is already set to 1). It is set to 1 regardless of the
Real Time Clock Enable bit (bit 2 of PM1_EN_HIGH
register). It is reset by software, as described above.
Upon first power up, this bit may be 1
This bit is set to 1 when the SWITCH input pin is 0 for
over 3.95 or 4 seconds (as selected by bit 3 of APCR7),
i.e., when the user presses the power button for more
than 3.95 o r4 seconds. The SWITCH state is detected
after the debouncer.
FIGURE 4-33. PM1_STS_HIGH Register Bitmap
WAK_STS
6
0
Power Management 1 Status High Byte
Register (PM1_STS_HIGH)
0
5
0
4
Reserved
0
3
PWRBTNOR_STS
X
2
0
RTC_STS
1
Power Management 1 Status
0
Reserved
0
Power-Up
Reset
Required
PWRBTN_STS
High Byte Register
(PM1_STS_HIGH)
Offset 01h