pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 76

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

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Bits 5-3 -GPIO13 Event Polarity/Edge Select
Bits 7,6 - Extended Wakeup options after Power Failure.
4.5.14 APC Control Register 7 (APCR7)
This register contains the P12 event polarity/edge settings,
the Power Button Override time and the Power Supply Pro-
tect Mode bit.
Upon first Power-Up this register is reset to 05h. The bit set-
tings are unaffected by Master Reset.
APCR6
Bits
7 6
0 0
0 1
1 0
1 1
These bits determine the physical conditions that trigger
the GPIO13 Event.
These bits are unaffected by Master Reset.
These bits determine the system wake-up behavior af-
ter return from Power failure, as follows:
TABLE 4-17. Extended Wake-up Option settings
TABLE 4-16. GPIO13 Event settings select
APCR6 bits
The MOAP bit (bit 4, APCR1) determines
system response upon return from power failure
While the Power Failure bit (bit 7, APCR1) is
set, mask ONCTL activation except if a new
enabled event occurs after power returns.
While the Power Failure bit (bit 7, APCR1) is
set, mask ONCTL activation except:
Reserved
5 4 3
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
if a MATCH event occurred during power
failure
if a new enabled event occurs after power
returns
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
Physical trigger condition
Low level
High level
Reserved
Falling Edge
Rising Edge
Falling or Rising Edge
Wake up Option
76
Bits 2-0 - P12 Event Polarity/Edge Select
Bit 3 - Power Button Override Time Select
(PWRBTNOR)
Bit 4 - Power Supply Protect Mode
Bits 7-5 - Reserved
0
7
These bits determine the physical conditions that trigger
the P12 event.
Note that P12 is multiplexed with the CS0. In any case,
it is the internal P12 port’s output that is detected.
This bit selects the Power Button Override time.
0: 4 seconds override time select.
1: 3.95 seconds override time select
0: ONCTL can be asserted only after 1 second
1: ONCTL can be asserted immediately after it was
6
0
passed since it was deasserted.
When for the last 500 msec ONCTL is asserted but
Vdd does not exist, ONCTL is deasserted.
deasserted.
The case in which Vdd does not exist for 500 msec
has no affect on ONCTL.
FIGURE 4-27. APCR7 Register Bitmap
APCR7 bits
TABLE 4-18. P12 Event settings select
5
0
Reserved
2 1 0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
4
Power Supply Protect Mode
0
3
2
1
PWRBTNOR
Physical trigger condition
Low level
High level
Reserved
Falling Edge
Rising Edge
Falling or Rising Edge
0
1
1
0
P12 Event Polarity/Edge select
Power-Up
Reset
Required
APC Control
Register 7
Index 4Dh
(APCR7)
Bank 2,