pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 38

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

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Bit 4 - X-Bus Data Buffer (XDB) Select
Bit 5 - Lock Scratch Bit
Bits 7,6 - General Purpose Scratch Bits
2.4.4
This read/write register is reset by hardware to 00h-03h.
See BADDR1,0 strap pins in Section 2.1.3 "The Strap Pins"
on page 28.
Bits 1,0 - BADDR1 and BADDR0
Bit 2 - GPIO22 or POR Pin Select
Bits 4,3 - GPIO21, IRSL2/ID2 or IRSL0 Pin Select
0
7
Select X-bus buffer on the XDB pins. This read only bit
is initialized with the CFG1 strap value. See TABLE 2-21
and see also Chapter 11 "X-Bus Data Buffer" on page
229.
0: No XDB buffer. XDB pins have alternate function,
1: XDB enabled.
This bit controls bits 7 and 6 of this register. Once this
bit is set to 1 by software, it can be cleared to 0 only by
a hardware reset.
0: Bits 7 and 6 of this register are read/write bits.
1: Bits 7 and 6 of this register are read only bits.
When bit 5 is set to 1, these bits are read only. After re-
set they can be read or written. Once changed to read-
only, they can be changed back to be read/write bits
only by a hardware reset.
Initialized on reset by BADDR1 and BADDR0 strap pins
(BADDR0 on bit 0). These bits select the addresses of
the configuration Index and Data registers and the Plug
and Play ISA Serial Identifier. See TABLE 2-1 "Base
Addresses" on page 27 and TABLE 2-2 "The Strap
Pins" on page 28.
The output buffer of this pin is selected by Port 2 Output
Type and Port 2 Pull-up Control registers.
0: The pin is GPIO22.
1: The pin is POR.
The output buffer of this pin is selected by Port 2 Output
Type and Port 2 Pull-up Control registers as shown in
TABLE 2-22 "Signal Assignment for Pins 158 and 77".
GPIO Bank Select
0
6
see TABLE 1-2
(XDB) Pins" on page 25.
SuperI/O Configuration 2 Register (SIOC2)
GPIO17 or WDO Pin Select
FIGURE 2-4. SIOC2 Register Bitmap
0
5
GPIO20 or IRSL1 Pin Select
0
4
0
3
GPIO21, IRSL2/ ID2 or ISL0 Pin Select
0
2
GPIO22 or POR Select
x
1
"Multiplexed X-Bus Data Buffer
x
0
SuperI/O Configuration 2
Reset
Required
BADDR1 and BADDR0
Register (SIOC2),
Index 22h
Configuration
38
Bit 5 - GPIO20, IRSL1 or ID1 Pin Select
Bit 6 - GPIO17 or WDO Pin Select
Bit 7 - GPIO Bank Select
2.4.5
This read/write register is reset by hardware to 00h. It indi-
cates the index of one of the Programmable Chip Select
(CS0, CS1 or CS2) configuration registers described in
Section 2.10 "PROGRAMMABLE CHIP SELECT CONFIG-
URATION REGISTERS" on page 42.
The data in the indicated register is in the Programmable
Chip Select Configuration Data register at index 24h.
Bits 7 through 4 are read only and return 0000 when read.
FIGURE 2-5. Programmable Chip Select Configuration
TABLE 2-22. Signal Assignment for Pins 158 and 77
0
0
7
Bits
0 0
0 1
1 0
1 1
4 3
The output buffer of this pin is selected by Port 2 Output
Type and Port 2 Pull-up Control registers.
0: The pin is GPIO20.
1: The pin is IRSL1/ID1.
This bit determines whether GPIO17 or WDO is routed
to pin 156 when bit 7 of the Port 1 Direction register at
offset 01h of logical device 7 is set to 1. See Section 9.1
"GPIO PORT ACTIVATION" on page 215.
The output buffer of this pin is selected by Port 2 Output
Type and Port 2 Pull-up Control registers.
0: GPIO17 uses the pin. (Default)
1: WDO uses the pin.
This bit selects the active register bank of GPIO registers.
0: Bank 0 is selected. (Default)
1: Bank 1 is selected.
0
0
6
Programmable Chip Select Configuration Index
Register
0
0
5
IRSL2/ID2
Reserved
GPIO21
Read Only
Pin 158
IRSL0
0
0
4
0
Index Register Bitmap
3
0
2
0
1
Index of a Programmable
Chip Select Configuration
Register
0
(When Bit 4 of SuperI/O
0
Programmable Chip Select
Config 1 Register = 0)
Reset
Required
GPIO21/SELCS
IRSL2/SELCS
IRSL2/SELCS
IRSL2/SELCS
Configuration Index
Pin 77
Index 23h
Register,