pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 70

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

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The APC registers are not affected by Master Reset. They
are initialized to 0 only when power is applied for the first
time, i.e., application of one of the voltages V
when no previous voltage was present.
4.5.1
Bit 0 - Fail-safe Timer Trigger Command
Bit 1 - Switch Off Delay Option
Bit 2 - POR Edge or Level Select
Bit 3 - Level POR Clear Command
Bit 4 - Mask ONCTL Activation if Power Fail (MOAP)
Bit 5 - Software Off Command (SOC)
Bit 6 - Fail-safe Timer Reset Command
7
0
This write-only bit returns 0 when read. Writing a 1 to
this bit resets the failsafe timer and triggers a 5 or 21
second countdown, as selected by bit 1 of this register.
0: Ignored.
1: 5 or 21 second failsafe countdown triggered.
0: 5 seconds.
1: 21 seconds.
0: Edge POR.
1: Level POR. Once POR is asserted, it remains as-
This is a write-only non-sticky bit. Read returns 0.
0: Ignored.
1: POR output signal is deactivated.
The function of this bit is enabled by extended wakeup
options settings in APCR6, bits 6 and 7.
0: When power returns and APCR6 bit 6 and 7 are
1: While the Power Failure bit (bit 7 of APCR1) is set,
This bit is write-only and non-sticky. Read returns 0.
0: Ignored.
1: ONCTL output signal is deactivated.
This bit is write-only and non-sticky. Read returns 0.
Power Failure
6
0
serted until cleared by Level POR Clear Command
(bit 3).
00, sets the system to the power state that existed
when power failed.
mask ONCTL activation, except as a result of a
Switch On Event.
APC Control Register 1 (APCR1)
FIGURE 4-14. APCR1 Register Bitmap
Fail-safe Timer Reset Command
5
0
SOC
4
0
3
0
MOAP
Level POR Clear Command
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
2
0
POR Edge or Level Select
1
0
Switch Off Delay Option
0
0
Power-Up
Reset
Required
Failsafe Timer Trigger Cmd.
APC Control
BAT
Register 1
Index 40h
(APCR1)
Bank 2
or V
CCH
70
Bit 7 - Power Failure
4.5.2
Bit 0 - Timer Match Enable (TME)
Bit 1 - RING Source Select (RSS)
Bit 2 - RING Pulse or Train Detection Mode (RPTDM)
Bit 3 - RING Enable (RE)
Bit 4 - RI1 Enable (R1E)
Bit 5 - RI2 Enable (R2E)
0
7
0: Ignored.
1: Fail-safe timer is stopped and reset.
Set to 1 when RTC/APC switches from V
Cleared to 0 by writing 1 to this bit. Writing 0 to this bit
has no effect.
0: Pre-determined date or time event is ignored.
1: Match between the RTC and the pre-determined
0: RING source is RING/XDCS signal, regardless of
1: RING source is GPIO23/RING signal.
0: Detection of RING pulse falling edge.
1: Detection of RING pulse train above 16 Hz for 0.19
0: RING input signal is ignored.
1: RING detection activates the ONCTL output signal,
0: RI1 input signal is ignored.
1: A high to low transition on the RI1 input pin acti-
0: RI2 input signal is ignored.
1: A high to low transition on the RI2 input pin acti-
6
0
Software On Command
date and time activates the ONCTL output signal.
See MOAP (bit 4) of APCR1 and APCR6 bit 6,7 for
an overriding case.
X-bus Data Buffer (XDB) select bit of SuperI/O
Configuration 1 register.
sec.
unless it is overridden by the MOAP bit, bit 4 of the
APCR1 register and bits 6,7 0f APCR6.
vates the ONCTL output pin.
See MOAP (bit 4) of APCR1 and APCR6 bit 6,7 for
an overriding case.
vates the ONCTL output pin.
APC Control Register 2 (APCR2)
FIGURE 4-15. APCR2 Register Bitmap
5
SODE
0
4
0
R2E
0
3
R1E
0
2
RE
0
1
RPTDM
0
0
RSS
Power-Up
Reset
Required
TME
APC Control
CCH
Register 2
Index 41h
(APCR2)
Bank 2
to V
BAT
.