pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 176

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

www.national.com
7.11.11 Auxiliary Status and Control Register (ASCR)
This register shares a common address with the previous
one (SCR).
This register is accessed when the Extended mode of op-
eration is selected. The definition of the bits in this case is
dependent upon the mode selected in the MCR register,
bits 7 through 5. This register is cleared upon hardware re-
set Bits 2 and 6 are cleared when the transmitter is “soft re-
set”. Bits 0,1,4 and 5 are cleared when the receiver is “soft
reset”.
Bit 0 - RX_FIFO Time-Out (RXF_TOUT)
Bit 1 -Reserved
Bit 2 - Set End of Transmission (S_EOT)
0
0
7
7
This bit is read only and set to 1 when an RX_FIFO tim-
eout occurs. It is cleared when a character is read from
the RX_FIFO.
Read/Write 0.
In Consumer-IR mode this is the Set End of Transmis-
sion bit. When a 1 is written into this bit position before
writing the last character into the TX_FIFO, data trans-
mission is gracefully completed.
In this mode, if the CPU simply stops writing data into
the TX_FIFO at the end of the data stream, a transmitter
underrun is generated and the transmitter stops. In this
Reserved
0
6
6
0
TXUR
FIGURE 7-18. ASCR Register Bitmap
5
5
FIGURE 7-17. SPR Register Bitmap
RXACT
0
4
4
RXWDG
0
0
3
3
Non-Extended Modes
Reserved
0
Extended Modes
2
2
Scratch Data
0
0
S_EOT
1
1
Reserved
0
0
0
Reset
Required
RXF_TOUT
Reset
Required
Enhanced Serial Port with IR - UART2 (Logical Device 5)
Scratchpad Register
Register (ASCR)
Auxiliary Status
Offset 07h
Offset 07h
Bank 0,
Bank 0,
(SCR)
176
Bit 3 - Reserved
Bit 4 - Reception Watchdog (RXWDG)
Bit 5 - Receiver Active (RXACT)
Bit 6 - Infrared Transmitter Underrun (TXUR)
Bit 7 - Reserved
7.12 BANK 1 – THE LEGACY BAUD GENERATOR
This register bank contains two Baud Generator Divisor
Ports, and a bank select register.
The Legacy Baud Generator Divisor (LBGD) port provides
an alternate path to the Baud Divisor Generator register.
This bank is implemented to maintain compatibility with
16550 standard and to support existing legacy software
packages. In case of using legacy software, the addresses
0 and 1 are shared with the data ports RXD/TXD (see page
166). The selection between them is controlled by the value
of the BKSE bit (LCR bit 7 page 171).
04h - 07h
Offset
case this is not an error, but the software must clear the
underrun before the next transmission can occur. This
bit is automatically cleared by hardware when a charac-
ter is written to the TX_FIFO.
Read/Write 0.
In Consumer-IR mode, this is the Reception Watchdog
(RXWDG) bit. It is set to 1 each time a pulse or pulse-
train (modulated pulse) is detected by the receiver. It
can be used by the software to detect a receiver idle
condition. It is cleared upon read.
In Consumer-IR Mode this is the Receiver Active (RX-
ACT) bit. It is set to 1 when an infrared pulse or pulse-
train is received. If a 1 is written into this bit position, the
bit is cleared and the receiver is deactivated. When this
bit is set, the receiver samples the infrared input contin-
uously at the programmed baud and transfers the data
to the RX_FIFO. See “Consumer-IR Reception” on
page 164.
In the Consumer-IR mode, this is the Transmitter Un-
derrun flag. This bit is set to 1 when a transmitter under-
run occurs. It is always cleared when a mode other than
Consumer-IR is selected. This bit must be cleared, by
writing 1 into it, to re-enable transmission.
Read/Write 0.
00h
01h
02h
03h
DIVISOR PORTS
TABLE 7-11. Bank 1 Register Set
LBGD(H) Legacy Baud Generator Divisor
Register
LBGD(L)
Name
LCR/
BSR
Legacy Baud Generator Divisor
Bank Select Register
Reserved
Reserved
Port (High Byte)
Port (Low Byte)
Link Control /
Description