pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 152

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

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6.5.14 ECP Extended Data Register (EDR)
This read/write register is the data port of the control regis-
ter indicated by the index stored in the EIR. Reading or writ-
ing this register reads or writes the data in the control
register whose second level offset is specified by the EIR.
Bits 7-0 - Data Bits
6.5.15 ECP Extended Auxiliary Status Register (EAR)
Upon reset, this register is initialized to 00h.
Bits 6-0 - Reserved
Bit 7 - FIFO Tag
0
0
7
7
These read/write data bits transfer data to and from the
Control Register pointed at by the EIR register.
Read only. In mode 011, when bit 5 of the DCR is 1
(backward direction), this bit reflects the value of the tag
bit (BUSY status) of the word currently in the bottom of
the FIFO.
In other modes this bit is indeterminate.
FIFO Tag
D7
0
0
6
6
D6
0
0
5
FIGURE 6-28. EDR Register Bitmap
5
FIGURE 6-29. EAR Register Bitmap
D5
0
0
4
4
D4
0
0
3
3
D3
Reserved
0
0
2
2
D2
Data Bits
0
0
1
1
D1
0
0
0
0
Reset
Required
D0
Reset
Required
ECP Extended Auxiliary
Status Register (EAR)
ECP Extended Data
Register (EDR)
Parallel Port (Logical Device 4)
Offset 404h
Offset 405h
152
6.5.16 Control0 Register
Upon reset, this register is initialized to 00h.
Bit 0 - EPP Time-Out Interrupt Mask
Bit 3-1 - Reserved
Bit 4 - Freeze Bit
Bit 5 - DCR Register Live
Bits 7, 6 - Reserved
6.5.17 Control2 Register
Upon reset, this register is initialized to 00h.
0
7
0
7
0: The EPP time-out is masked.
1: The EPP time-out is generated.
In mode 011, setting this bit to 1 freezes part of the in-
terface with the peripheral device, and clearing this bit to
0 releases and initializes it.
In all other modes the value of this bit is ignored.
When this bit is 1, reading DCR (see Section 6.5.6 "ECP
Control Register (DCR)" on page 148) reads the inter-
face control lines pin values regardless of the mode se-
lected.
Otherwise, reading the DCR reads the content of the
register.
Reserved
SPP Compatability
0
6
0
6
FIGURE 6-30. Control0 Register Bitmap
FIGURE 6-31. Control2 Register Bitmap
Reserved
0
5
0
5
Channel Address Enable
DCR Register Live
0
Reserved
4
0
4
Freeze Bit
0
3
Revision 1.7 or 1.9 Select
0
3
Reserved
EPP 1.7 ZWS Control
0
2
0
2
Reserved
Reserved
0
1
0
1
Reserved
0
Reserved
0
0
0
Reset
Required
EPP Time-Out
Interrupt Mask
Reset
Required
Reserved
Control0 Register
Control2 Register
Second Level
Second Level
Offset 00h
Offset 02h