pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 151

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

Bit 3 - ECP DMA Enable
Bit 4 - ECP Interrupt Mask
Bits 7-5 - ECP Mode Control
6.5.13 ECP Extended Index Register (EIR)
The parallel port is partially configured by bits within the log-
ical device address space. These configuration bits are ac-
cessed via this read/write register and the Extended Data
Register (EDR) (see Section 6.5.14 "ECP Extended Data
Register (EDR)" on page 152), when bit 4 of the SuperI/O
Bit 7
0: The DMA and the above interrupts are not dis-
1: The DMA and the above three interrupts are dis-
0: The DMA request signal (DRQ3-0) is set to TRI-
1: The DMA is enabled and the DMA starts when bit 2
0: An interrupt is generated on ERR assertion (the
1: No interrupt is generated.
These bits set the mode for the ECP device. See Sec-
tion 6.6 "DETAILED ECP MODE DESCRIPTIONS" on
page 154 for a more detailed description of operation in
each of these ECP modes. The ECP modes are listed in
TABLE 6-9 "ECP Modes Encoding" and described in
detail in TABLE 6-11 "ECP Modes" on page 155.
0
0
0
0
1
1
1
ECR Bit Encoding
abled.
abled.
STATE and the appropriate acknowledge signal
(DACK3-0) is assumed inactive.
of ECR is 0.
high-to-low edge of ERR). An interrupt is also gen-
erated while ERR is asserted when this bit is
changed from 1 to 0; this prevents the loss of an in-
terrupt between ECR read and ECR write.
TABLE 6-9. ECP Modes Encoding
Bit 6
0
0
1
1
0
1
1
Bit 5
0
1
0
1
0
0
1
Parallel Port FIFO
Configuration
Mode Name
EPP Mode
ECP FIFO
FIFO Test
Standard
PS/2
Parallel Port (Logical Device 4)
151
Parallel Port Configuration register at index F0h of logical
device 4 is set to 1. See Section 2.7.1 "SuperI/O Parallel
Port Configuration Register" on page 41.
The configuration bits within the parallel port address space
are initialized to their default values on reset, and not when
the parallel port is activated.
Bits 2-0 - Second Level Offset
Bits 7-3 - Reserved
0
Second Level
7
Data written to these bits is used as a second level off-
set for accesses to a specific control register. Second
level offsets of 00h, 02h, 04h and 05h are supported. At-
tempts to access registers at any other offset have no
effect.
000:Access the Control0 register.
010:Access the Control2 register.
100:Access the Control4 register.
101:Access the PP Confg0 register.
These bits are treated as 0 for offset calculations. Writ-
ing any other value to them has no effect.
These bits are read only. They return 00000 on reads
and must be written as 00000.
Reserved
0
6
Offset
00h
02h
04h
05h
Reserved
0
5
FIGURE 6-27. EIR Register Bitmap
TABLE 6-10. Second Level Offsets
Reserved
0
4
Reserved
0
3
Register Name
Reserved
PP Confg0
0
2
Control0
Control2
Control4
Control
0
1
0
Second Level Offset
0
Reset
Required
ECP Extended Index
6.5.16 on page 152
6.5.17 on page 152
6.5.18 on page 153
6.5.19 on page 153
Described in
Section
Register (EIR)
Offset 403h
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