pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 177

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

In addition, a fallback mechanism maintains this compatibil-
ity by forcing the UART to revert to 16550 mode if 16550
software addresses the module after a different mode was
set. Since setting the Baud Divisor values is a necessary ini-
tialization of the 16550, setting the divisor values in bank 1
forces the UART to enter 16550 mode. (This is called fall-
back.)
To enable other modes to program their desired baud rates
without activating this fallback mechanism, the Baud Gen-
erator Divisor Port pair in bank 2 should be used.
7.12.1 Legacy Baud Generator Divisor Ports (LBGD(L)
The programmable baud rates in the Non-Extended mode
are achieved by dividing a 24 MHz clock by a prescale value
of 13, 1.625 or 1. This prescale value is selected by the
PRESL field of EXCR2 (see page 180). This clock is subdi-
vided by the two Baud Generator Divisor buffers, which out-
put a clock at 16 times the desired baud (this clock is the
BOUT clock). This clock is used by I/O circuitry, and after a
last division by 16 produces the output baud.
Divisor values between 1 and 2
forbidden). The Baud Generator Divisor must be loaded
during initialization to ensure proper operation of the Baud
Generator. Upon loading either part of it, the Baud Genera-
tor counter is immediately loaded. Table 7-15 on page 179
shows typical baud divisors. After reset the divisor register
contents are indeterminate.
Any access to the LBGD(L) or LBGD(H) ports causes a re-
set to the default Non-Extended mode, i.e., 16550 mode
(See “AUTOMATIC FALLBACK TO A NON-EXTENDED
UART MODE” on page 165).To access a Baud Generator
Divisor when in the Extended mode, use the port pair in
bank 2 (BGD on page 178).
Table 7-12 shows the bits which are cleared when Fallback
occurs during Extended or Non-Extended modes.
If the UART is in Non-Extended mode and the LOCK bit is
1, the content of the divisor (BGD) ports will not be affected
and no other action is taken.
When programming the baud, the new divisor is loaded
upon writing into LBGD(L) and LBGD(H). After reset, the
contents of these registers are indeterminate.
Divisor values between 1 and 2
forbidden.) Table 7-14 shows typical baud divisors.
Register
EXCR1
EXCR2
IRCR1
MCR
and LBGD(H)),
TABLE 7-12. Bits Cleared On Fallback
LOCK = x
Extended
0, 5 and 7
2 and 3
UART Mode & LOCK bit before Fallback
Mode
2 to 7
0 to 5
Non-Extended
LOCK = 0
5 and 7
0 to 5
Mode
none
none
Enhanced Serial Port with IR - UART2 (Logical Device 5)
16
16
-1 can be used. (Zero is
-1 can be used. (Zero is
Non-Extended
LOCK = 1
Mode
none
none
none
none
177
.
.
7.12.2 Link Control Register (LCR) and Bank Select
These registers are the same as the registers at offset 03h
in bank 0.
7.13 BANK 2 – EXTENDED CONTROL AND STATUS
Bank 2 contains two alternate Baud Generator Divisor ports
and the Extended Control Registers (EXCR1 and EXCR2).
Offset
7
7
00h
01h
02h
03h
04h
05h
06h
07h
REGISTERS
6
6
FIGURE 7-20. LBGD(H) Register Bitmap
FIGURE 7-19. LBGD(L) Register Bitmap
Register (BSR)
5
5
LCR/BSR
Register
BGD(H)
BGD(L)
EXCR1
EXCR2
TXFLV
RXFLV
TABLE 7-13. Bank 2 Register Set
Name
4
4
3
3
Most Significant Byte
2
2
Least Significant Byte
Link Control/ Bank Select Register
Baud Generator Divisor Port (High
Baud Generator Divisor Port (Low
Legacy Baud Generator Divisor
Legacy Baud Generator Divisor
Extended Control Register 1
Extended Control Register 2
1
1
of Baud Generator
of Baud Generator
Reserved
0
0
Reset
Required
Reset
Required
RX_FIFO Level
TX_FIFO Level
Description
byte)
byte)
High Byte port
Low Byte port
(LBGD(L))
Offset 00h
Offset 01h
(LBGD(H))
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Bank 1,
Bank 1,