pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 42

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

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2.8 UART2 AND INFRARED CONFIGURATION
2.8.1
This read/write register is reset by hardware to 02h.
FIGURE 2-13. SuperI/O UART2 Configuration Register
Bit 0 - TRI-STATE Control for UART signals
Bit 1 - Power Mode Control
Bit 2 - Busy Indicator
Bit 3 - Ring Detection on RI Pin
0
7
This bit controls the TRI-STATE status of UART signals
(except IRQ and DMA signals) when the UART is inac-
tive (disabled). This bit is ORed with a bit of the PMC1
register of the power management device (logical de-
vice 8).
0: Signals not in TRI-STATE.
1: Signals in TRI-STATE.
0: Low power mode.
1: Normal power mode.
This read-only bit can be used by power management
software to decide when to power down the logical de-
vice. This bit is also accessed via the PMC3 register of
the power management device (logical device 8).
0: No transfer in progress.
1: Transfer in progress.
0: The UART RI input signal uses the RI pin.
1: The UART RI input signal is the RING detection
REGISTER (LOGICAL DEVICE 5)
0
Bank Select Enable
6
UART Clock disabled. UART output signals are set
to their default state. The RI input signal can be
programmed to generate an interrupt. Registers
are maintained.
UART clock enabled. The UART is functional when
the logical device is active. This bit is ANDed with a
bit of the PMC3 register of the power management
device (logical device 8)
signal on the RING pin. RING pin is selected by the
APCR2 register of the Advanced Power Control
(APC) module.
SuperI/O UART2 Configuration Register
0
5
0
4
Reserved
0
3
Ring Detection on RI Pin
0
2
Busy Indicator
1
1
Bitmap
Power Mode Control
0
0
Reset
Required
TRI-STATE Control for
UART2 Signals
Configuration Register,
SuperI/O UART2
Index F0h
Configuration
42
Bits 6-4 - Reserved
Bit 7 - Bank Select Enable
2.9 UART1 CONFIGURATION REGISTER
2.9.1
This read/write register is reset by hardware to 02h. Its bits func-
tion like the bits in the SuperI/O UART2 Configuration register
FIGURE 2-14. SuperI/O UART1 Configuration Register
2.10 PROGRAMMABLE CHIP SELECT
The chip select configuration registers are accessed using
two index levels. The first index level accesses the Program-
mable Chip Select Index register at 23h. See Section 2.4.5
"Programmable Chip Select Configuration Index Register"
on page 38. The second index level accesses a specific chip
select configuration register as shown in TABLE 2-24 "The
Programmable Chip Select Configuration Registers".
See also Section 9.3 "PROGRAMMABLE CHIP SELECT
OUTPUT SIGNALS" on page 216 and the description of
each signal in TABLE 1-1 "Signal/Pin Description Table" on
page 17.
0
7
Enables bank switching. If this bit is cleared, all attempts
to access the extended registers are ignored.
(LOGICAL DEVICE 6)
CONFIGURATION REGISTERS
0
Bank Select Enable
6
SuperI/O UART1 Configuration Register
0
5
0
4
Reserved
0
3
Ring Detection on RI Pin
0
2
Busy Indicator
1
1
Bitmap
Power Mode Control
0
0
Reset
Required
TRI-STATE Control for
UART1 Pins
Configuration Register,
SuperI/O UART1
Index F0h