pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 127

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

5.7.14 The RECALIBRATE Command
The RECALIBRATE command issues pulses that make the
head of the selected drive step out until it reaches track 0.
Command Phase
Second Command Phase Byte
Execution Phase
After the last command byte is issued, the Drive Busy bit for
the selected drive is set in the Main Status Register (MSR).
See bits 3-0 in Section 5.3.5 "Main Status Register (MSR)"
on page 100.
The controller waits the Delay Before Processing time (see
TABLE 5-25 "Constant Multipliers for Delay Before Pro-
cessing Factor and Delay Ranges" on page 132) for the se-
lected drive., and then becomes idle. See Section 5.4.4
"Idle Phase" on page 106.
Then, the controller issues pulses until the TRK0 disk inter-
face input signal becomes active or until the maximum num-
ber of RECALIBRATE step pulses have been issued.
TABLE 5-20 "Maximum RECALIBRATE Step Pulses for
Values of R255 and ETR" shows the maximum number of
RECALliBRATE step pulses that may be issued, depending
on the RECALIBRATE Step Pulses (R255) bit, bit 0 in the
second command phase byte of the MODE command
(page 119), and the Extended Track Range (ETR) bit, bit 4
of the third command byte of the MODE command (see
Section 5.7.7 "The MODE Command" on page 119).
If the number of tracks on the disk drive exceeds the maxi-
mum number of RECALIBRATE step pulses, it may be nec-
essary to issue another RECALIBRATE command.
TABLE 5-20. Maximum RECALIBRATE Step Pulses for
X
7
7
0
R255
See “Second Command Phase Byte” on page 116 for a
description of the Drive Select (DS1,0) and Head Select
(HD) bits.
0
1
0
1
X
6
6
0
ETR
0
0
1
1
Values of R255 and ETR
X
5
5
0
Bytes-Per-Sector Code
Sector Number
Head Number
RECALIBRATE Step Pulses
X
4
4
0
Maximum Number of
X
3
3
0
85 (default)
3925
4095
255
HD
2
2
1
DS1
1
1
1
DS0
0
0
1
127
The pulses actually occur while the controller is in the drive
polling phase. See Section 5.4.5 "Drive Polling Phase" on
page 106.
An interrupt is generated after the TRK0 signal is asserted,
or after the maximum number of RECALIBRATE step puls-
es is issued.
Software should ensure that the RECALIBRATE command
is issued for only one drive at a time. This is because the
drives are actually selected via the Digital Output Register
(DOR), which can only select one drive at a time.
No command, except a SENSE INTERRUPT command,
should be issued while a RECALIBRATE command is in
progress.
Result Phase
None.
5.7.15 The RELATIVE SEEK Command
The RELATIVE SEEK command issues STEP pulses that
make the head of the selected drive step in or out a pro-
grammable number of tracks.
Command Phase
First Command Phase Byte, Opcode,
Bit - 6 Step Direction DIR
Second Command Phase Byte
Third Command Phase Byte - Relative Track Number
(RTN)
Execution Phase
After the last command byte is issued, the Drive Busy bit for
the selected drive is set in the Main Status Register (MSR).
See bits 3-0 in Section 5.3.5 "Main Status Register (MSR)"
on page 100.
The controller waits the Delay Before Processing time (see
TABLE 5-25 "Constant Multipliers for Delay Before Pro-
cessing Factor and Delay Ranges" on page 132) for the se-
lected drive., and then becomes idle. See Section 5.4.4
"Idle Phase" on page 106.
Then, the controller enters the idle phase and issues RTN
STEP pulses until the TRK0 disk interface input signal be-
comes active or until the specified number (RTN) of STEP
pulses have been issued. After the RELATIVE SEEK oper-
ation is complete, the controller generates an interrupt.
X
7
1
This bit defines the step direction.
0: Step head out.
1: Step head in.
See “Second Command Phase Byte” on page 116 for a
description of the Drive Select (DS1,0) and Head Select
(HD) bits.
This value specifies how many tracks the head should
step in or out from the current track.
DIR
X
6
Relative Track Number (RTN)
X
5
0
X
4
0
X
3
1
HD
2
1
DS1
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1
1
DS0
0
1