pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 202

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

www.national.com
Bits 2 - Number of Stop Bits (STB)
Bit 3 - Parity Enable (PEN)
Bit 4 - Even Parity Select (EPS)
Bit 5 - Stick Parity (STKP)
Bit 6 - Set Break (SBRK)
This bit specifies the number of stop bits transmitted
with each serial character.
0: One stop bit is generated. (Default)
1: If the data length is set to 5-bits via bits 1,0
This bit enable the parity bit See Table 8-7 on page 202.
The parity enable bit is used to produce an even or odd
number of 1s when the data bits and parity bit are
summed, as an error detection device.
0: No parity bit is used. (Default)
1: A parity bit is generated by the transmitter and
When Parity is enabled (PEN is 1), this bit, together with
bit 5 (STKP), controls the parity bit as shown in Table
8-7.
0: If parity is enabled, an odd number of logic 1s are
1: If parity is enabled, an even number of logic 1s are
When Parity is enabled (PEN is 1), this bit, together with
bit 4 (EPS), controls the parity bit as show in Table 8-7.
This bit enables or disables a break. During the break,
the transmitter can be used as a character timer to ac-
curately establish the break duration.
PEN
WLS1
0
1
1
1
1
TABLE 8-6. Word Length Select Encoding
TABLE 8-7. Bit Settings for Parity Control
(WLS1,0), 1.5 stop bits are generated. For 6, 7 or 8
bit word lengths, two stop bits are transmitted. The
receiver checks for one stop bit only, regardless of
the number of stop bits selected.
checked by the receiver.
transmitted or checked in the data word bits and
parity bit. (Default)
transmitted or checked.
0
0
1
1
EPS
x
0
1
0
1
WLS0
0
1
0
1
STKP
x
0
0
1
1
Character Length
Selected Parity Bit
Enhanced Serial Port - UART1 (Logical Device 6)
5 (Default)
Logic 1
Logic 0
6
7
8
None
Even
Odd
202
Bit 7 - Bank Select Enable (BKSE)
8.5.6
The Bank Selection Register (BSR) selects which register
bank is to be accessed next.
About accessing this register see the description of bit
7 of the LCR Register.
Bits 6-0 - Bank Selection
Bit 7 - Bank Selection Enable (BKSE)
0
7
This bit acts only on the transmitter front-end and has no
effect on the rest of the transmitter logic.
When set to 1 the SOUT pin is forced to a logic 0 state.
To avoid transmission of erroneous characters as a re-
sult of the break, use the following procedure to set
SBRK:
1. Wait for the transmitter to be empty. (TXEMP = 1).
2. Set SBRK to 1.
3. Wait for the transmitter to be empty, and clear SBRK
0: This register functions as the Line Control Register
1: This register functions as the Bank Select Register
When bit 7 is set to 1, bits 6-0 of BSR select the bank,
as shown in Table 8-8.
0: Bank 0 is selected.
1: Bits 6-0 specify the selected bank.
0
6
when normal transmission must be restored.
(LCR).
(BSR).
BKSE-Bank Selection Enable
Bank Selection Register (BSR)
0
5
FIGURE 8-11. BSR Register Bitmap
0
4
0
3
0
2
Bank Selection
0
1
0
0
Reset
Required
Bank Selection
Register (BSR)
Offset 03h
All Banks,