pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 216

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

www.national.com
(Index 49h, Bank 2, APC registers, Logical Device 2).
GPIO16 is selected by bit 0 of the APC Control Register 3
(Index 49h, Bank 2, APC registers, Logical Device 2).
GPIO24 is selected on GPIO24/XD2 by bit 4 of SuperI/O
Configuration 1 register (index 21h in the Card Control Reg-
isters). It is selected on GPIO24/IRRX1 by bit 3 of APC Con-
trol Register 3 (Index 49h, Bank 2, APC registers, Logical
Device 2). GPIO24 can be selected on both pins at the
same time: when configured as an output, its value will be
driven on both pins; when configured as an input, the value
of GPIO24/IRRX1 will be read and the value on
GPIO24/XD2 will be ignored.
GPIO25 is selected on GPIO25/XD3 by bit 4 of SuperI/O
Configuration 1 register (in the Card Control Registers). It is
selected on GPIO25/P16 by bit 0 of SuperI/O Configuration
3 register (in the Card Control Registers). GPIO25 can be
selected on both pins at the same time: when configured as
an output, its value will be driven on both pins; when config-
ured as an input, the value of GPIO25/P16 will be read and
the value on GPIO25/XD3 will be ignored.
GPIO30-32 and GPIO34-36 are selected by bit 3 of the Su-
perI/O Configuration 1 register (index 21h in the Card Con-
trol Registers).
GPIO33 is selected by bit 6 of the APC Control Register 5
(Index 4Bh, Bank 2, APC registers, Logical Device 2).
GPIO37 is selected by bit 4 of the APC Control Register 3
(Index 49h, Bank 2, APC registers, Logical Device 2).
Port 1 Data
Port 1 Direction
Port 1 Output Type
Port 1 Pull-up Control
Port 2 Data
Port 2 Direction
Port 2 Output Type
Port 2 Pull-up Control
GPIO Register
General Purpose Input and Output (GPIO) Ports (Logical Device 7) and Chip Select Output Signals
Offset
00h
01h
02h
03h
04h
05h
06h
07h
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TABLE 9-2. The GPIO Registers, Bank 0
Hard Reset
Value
FFh
00h
00h
FFh
FFh
00h
00h
FFh
Reads return the bit or pin value, according to the direction bit.
Writes are saved in this register and affect the output pins.
Each bit controls the direction of the corresponding port pin.
0: Input. Reads of Port Data register return pin value.
1: Output. Reads of Port Data register return bit value.
Each bit controls the type of the corresponding port pin.
0: Open-drain.
1: Push-pull.
Each bit controls the internal pull-up for the corresponding port pin.
0: No internal pull-up.
1: Internal pull-up.
Same as Port 1 Data register.
Same as Port 1 Direction register.
Same as Port 1 Output Type register.
Same as Port 1 Pull-up Control register.
216
9.3 PROGRAMMABLE CHIP SELECT OUTPUT
The three programmable chip select output signals have
the following characteristics:
Activation and deactivation (enabling and disabling) of these
chip select signals are controlled by the Function Enable
Register 2 (FER2) of logical device 8 (See Section 10.2.4
"Function Enable Register 2 (FER2)" on page 219) and the
configuration registers for CS0, CS1 and CS2 at second lev-
el indexes 02h, 06h and 0Ah, respectively.These registers
are accessed using two index levels.
The first level index points to the Programmable Chip Select
Index and Data registers, like other PC87317CS0, CS1 and
CS2 VUL configuration registers. See Sections 2.4.5 "Pro-
grammable Chip Select Configuration Index Register" and
2.4.6 "Programmable Chip Select Configuration Data Reg-
ister" on page 39. The Programmable Chip Select Configu-
ration Index and Data registers are at index 23h and 24h
respectively.
The second level points to one of the three registers for
each CS pin. See Section 2.10 "PROGRAMMABLE CHIP
SELECT CONFIGURATION REGISTERS" on page 42.
Each CS pin is configured by the three registers assigned
to it. One specifies the base address MSB. One specifies
the base address LSB and one configures the CS pin.
All 16 address bits are decoded, with five mask options to
ignore (not decode) address bits A0, A1, A2, A3 and A4-11.
Decoding of only address and AEN pins, without RD or WR
pins, is also supported.
A CS signal is asserted when an address match occurs and
may be qualified by RD or WR signal(s). An address match
occurs when the AEN signal is inactive (low) and the non-
masked address pins match the corresponding base ad-
dress bits.
CS0 is an open drain output signal.
CS1 and CS2 have push-pull buffers.
CS0 is in TRI-STATE when no V
SIGNALS
Description
DD
is applied.